Sagheer Ahmad

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
NoC buffer management for virtual channels
- Patent number 12,111,784
- Issue date Oct 8, 2024
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for secure deconstruction sensor in a heterogeneo...
- Patent number 12,093,394
- Issue date Sep 17, 2024
- Xilinx, Inc.
- Aman Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC with adaptive chip-to-chip interface to support different chip-t...
- Patent number 12,066,969
- Issue date Aug 20, 2024
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficiency and quality of service improvements for systems with hig...
- Patent number 12,047,275
- Issue date Jul 23, 2024
- Xilinx, Inc.
- Aman Gupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamically allocated buffer pooling
- Patent number 12,019,908
- Issue date Jun 25, 2024
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods to transport memory mapped traffic amongst inte...
- Patent number 12,019,576
- Issue date Jun 25, 2024
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed look-ahead routing in network-on-chip
- Patent number 11,985,061
- Issue date May 14, 2024
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive acceleration of transport layer security
- Patent number 11,983,264
- Issue date May 14, 2024
- Xilinx, Inc.
- Jaideep Dastidar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-use chip-to-chip interface
- Patent number 11,892,966
- Issue date Feb 6, 2024
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Localized NoC switching interconnect for high bandwidth interfaces
- Patent number 11,832,035
- Issue date Nov 28, 2023
- Xilinx, Inc.
- Aman Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip bump interface compatible with different orientations and type...
- Patent number 11,784,149
- Issue date Oct 10, 2023
- Xilinx, Inc.
- Ygal Arbel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Data bus inversion using multiple transforms
- Patent number 11,755,511
- Issue date Sep 12, 2023
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System-on-chip having multiple circuits and memory controller in se...
- Patent number 11,709,624
- Issue date Jul 25, 2023
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive integrated programmable device platform
- Patent number 11,683,038
- Issue date Jun 20, 2023
- Xilinx, Inc.
- Sagheer Ahmad
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
On-demand packetization for a chip-to-chip interface
- Patent number 11,636,061
- Issue date Apr 25, 2023
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Subsystem for configuration, security, and management of an adaptiv...
- Patent number 11,580,057
- Issue date Feb 14, 2023
- Xilinx, Inc.
- Ahmad R. Ansari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware-based virtual-to-physical address translation for programm...
- Patent number 11,327,899
- Issue date May 10, 2022
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and circuits for deadlock avoidance
- Patent number 11,281,618
- Issue date Mar 22, 2022
- XLNX, INC.
- Sagheer Ahmad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable network-on-chip for a programmable device
- Patent number 11,263,169
- Issue date Mar 1, 2022
- Xilinx, Inc.
- Ian Andrew Swarbrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip memory block circuit
- Patent number 11,182,110
- Issue date Nov 23, 2021
- Xilinx, Inc.
- Ahmad R. Ansari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive integrated programmable device platform
- Patent number 11,063,594
- Issue date Jul 13, 2021
- Xilinx, Inc.
- Sagheer Ahmad
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High bandwidth memory (HBM) bandwidth aggregation switch
- Patent number 10,916,516
- Issue date Feb 9, 2021
- Xilinx, Inc.
- Martin Newman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable network-on-chip for a programmable device
- Patent number 10,838,908
- Issue date Nov 17, 2020
- Xilinx, Inc.
- Ian A. Swarbrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Peripheral I/O device with assignable I/O and coherent domains
- Patent number 10,817,455
- Issue date Oct 27, 2020
- Xilinx, Inc.
- Jaideep Dastidar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware-based virtual-to-physical address translation for programm...
- Patent number 10,719,452
- Issue date Jul 21, 2020
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Domain assist processor-peer for coherent acceleration
- Patent number 10,698,842
- Issue date Jun 30, 2020
- Xilinx, Inc.
- Jaideep Dastidar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
End-to-end quality-of-service in a network-on-chip
- Patent number 10,673,745
- Issue date Jun 2, 2020
- Xilinx, Inc.
- Ian A. Swarbrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive integrated programmable device platform
- Patent number 10,673,439
- Issue date Jun 2, 2020
- Xilinx, Inc.
- Sagheer Ahmad
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High bandwidth chip-to-chip interface using HBM physical interface
- Patent number 10,410,694
- Issue date Sep 10, 2019
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inline ECC function for system-on-chip
- Patent number 10,346,346
- Issue date Jul 9, 2019
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
IIC WITH ADAPTIVE CHIP-TO-CHIP INTERFACE TO SUPPORT DIFFERENT CHIP-...
- Publication number 20240411715
- Publication date Dec 12, 2024
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BANDWIDTH THROUGH VERTICAL CONNECTIONS
- Publication number 20240387388
- Publication date Nov 21, 2024
- Xilinx, Inc.
- Brian C. GAIDE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROGRAMMABLE LOGIC FABRIC AS DIE TO DIE INTERCONNECT
- Publication number 20240313781
- Publication date Sep 19, 2024
- Xilinx, Inc.
- Brian C. GAIDE
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR SECURE DECONSTRUCTION SENSOR IN A HETEROGENEO...
- Publication number 20240281537
- Publication date Aug 22, 2024
- Xilinx, Inc.
- Aman GUPTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NOC ROUTING IN A MULTI-CHIP DEVICE
- Publication number 20240211422
- Publication date Jun 27, 2024
- Xilinx, Inc.
- Aman GUPTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCALIZED AND RELOCATABLE SOFTWARE PLACEMENT AND NOC-BASED ACCESS T...
- Publication number 20240211138
- Publication date Jun 27, 2024
- Xilinx, Inc.
- Aman Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-USE CHIP-TO-CHIP INTERFACE
- Publication number 20240176758
- Publication date May 30, 2024
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT TRANSACTION REDUNDANCY
- Publication number 20240111693
- Publication date Apr 4, 2024
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NOC BUFFER MANAGEMENT FOR VIRTUAL CHANNELS
- Publication number 20240111704
- Publication date Apr 4, 2024
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods to Transport Memory Mapped Traffic amongst inte...
- Publication number 20240045822
- Publication date Feb 8, 2024
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHIP BUMP INTERFACE COMPATIBLE WITH DIFFERENT ORIENTATIONS AND TYPE...
- Publication number 20240014161
- Publication date Jan 11, 2024
- Xilinx, Inc.
- Ygal ARBEL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM-ON-CHIP HAVING MULTIPLE CIRCUITS AND MEMORY CONTROLLER IN SE...
- Publication number 20230376248
- Publication date Nov 23, 2023
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK-ON-CHIP ARCHITECTURE FOR HANDLING DIFFERENT DATA SIZES
- Publication number 20230370392
- Publication date Nov 16, 2023
- Xilinx, Inc.
- Krishnan Srinivasan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
EFFICIENCY AND QUALITY OF SERVICE IMPROVEMENTS FOR SYSTEMS WITH HIG...
- Publication number 20230308384
- Publication date Sep 28, 2023
- Xilinx, Inc.
- Aman GUPTA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
FLEXIBLE QUEUE PROVISIONING FOR PARTITIONED ACCELERATION DEVICE
- Publication number 20230290189
- Publication date Sep 14, 2023
- Xilinx, Inc.
- Yanran CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE INTEGRATED PROGRAMMABLE DEVICE PLATFORM
- Publication number 20230291405
- Publication date Sep 14, 2023
- Xilinx, Inc.
- Sagheer Ahmad
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ADAPTIVE CHIP-TO-CHIP INTERFACE PROTOCOL ARCHITECTURE
- Publication number 20230244628
- Publication date Aug 3, 2023
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE ACCELERATION OF TRANSPORT LAYER SECURITY
- Publication number 20230177146
- Publication date Jun 8, 2023
- Xilinx, Inc.
- Jaideep DASTIDAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONIZATION OF SYSTEM RESOURCES IN A MULTI-SOCKET DATA PROCESSI...
- Publication number 20230153156
- Publication date May 18, 2023
- Xilinx, Inc.
- Karthik Shankar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-USE CHIP-TO-CHIP INTERFACE
- Publication number 20230141709
- Publication date May 11, 2023
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA BUS INVERSION USING MULTIPLE TRANSFORMS
- Publication number 20230069505
- Publication date Mar 2, 2023
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-DEMAND PACKETIZATION FOR A CHIP-TO-CHIP INTERFACE
- Publication number 20230066736
- Publication date Mar 2, 2023
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY ALLOCATED BUFFER POOLING
- Publication number 20230036531
- Publication date Feb 2, 2023
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCALIZED NOC SWITCHING INTERCONNECT FOR HIGH BANDWIDTH INTERFACES
- Publication number 20220337923
- Publication date Oct 20, 2022
- Xilinx, Inc.
- Aman GUPTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE NETWORK-ON-CHIP FOR A PROGRAMMABLE DEVICE
- Publication number 20210303509
- Publication date Sep 30, 2021
- Xilinx, Inc.
- Ian Andrew SWARBRICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUBSYSTEM FOR CONFIGURATION, SECURITY, AND MANAGEMENT OF AN ADAPTIV...
- Publication number 20210124711
- Publication date Apr 29, 2021
- Xilinx, Inc.
- Ahmad R. Ansari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERIPHERAL I/O DEVICE WITH ASSIGNABLE I/O AND COHERENT DOMAINS
- Publication number 20200327089
- Publication date Oct 15, 2020
- Xilinx, Inc.
- Jaideep Dastidar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE NETWORK-ON-CHIP FOR A PROGRAMMABLE DEVICE
- Publication number 20200026684
- Publication date Jan 23, 2020
- Xilinx, Inc.
- Ian A. Swarbrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE-BASED VIRTUAL-TO-PHYSICAL ADDRESS TRANSLATION FOR PROGRAMM...
- Publication number 20190391929
- Publication date Dec 26, 2019
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SUBSYSTEM FOR SYSTEM-ON-CHIP
- Publication number 20190250853
- Publication date Aug 15, 2019
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING

Sagheer Ahmad

Person

Patents Grantslast 30 patents

NoC buffer management for virtual channels

System and method for secure deconstruction sensor in a heterogeneo...

IC with adaptive chip-to-chip interface to support different chip-t...

Efficiency and quality of service improvements for systems with hig...

Dynamically allocated buffer pooling

Systems and methods to transport memory mapped traffic amongst inte...

Distributed look-ahead routing in network-on-chip

Adaptive acceleration of transport layer security

Multi-use chip-to-chip interface

Localized NoC switching interconnect for high bandwidth interfaces

Chip bump interface compatible with different orientations and type...

Data bus inversion using multiple transforms

System-on-chip having multiple circuits and memory controller in se...

Adaptive integrated programmable device platform

On-demand packetization for a chip-to-chip interface

Subsystem for configuration, security, and management of an adaptiv...

Hardware-based virtual-to-physical address translation for programm...

Methods and circuits for deadlock avoidance

Configurable network-on-chip for a programmable device

On-chip memory block circuit

Adaptive integrated programmable device platform

High bandwidth memory (HBM) bandwidth aggregation switch

Configurable network-on-chip for a programmable device

Peripheral I/O device with assignable I/O and coherent domains

Hardware-based virtual-to-physical address translation for programm...

Domain assist processor-peer for coherent acceleration

End-to-end quality-of-service in a network-on-chip

Adaptive integrated programmable device platform

High bandwidth chip-to-chip interface using HBM physical interface

Inline ECC function for system-on-chip

Patents Applicationslast 30 patents

IIC WITH ADAPTIVE CHIP-TO-CHIP INTERFACE TO SUPPORT DIFFERENT CHIP-...

MEMORY BANDWIDTH THROUGH VERTICAL CONNECTIONS

PROGRAMMABLE LOGIC FABRIC AS DIE TO DIE INTERCONNECT

SYSTEM AND METHOD FOR SECURE DECONSTRUCTION SENSOR IN A HETEROGENEO...

NOC ROUTING IN A MULTI-CHIP DEVICE

LOCALIZED AND RELOCATABLE SOFTWARE PLACEMENT AND NOC-BASED ACCESS T...

MULTI-USE CHIP-TO-CHIP INTERFACE

INTEGRATED CIRCUIT TRANSACTION REDUNDANCY

NOC BUFFER MANAGEMENT FOR VIRTUAL CHANNELS

Systems and Methods to Transport Memory Mapped Traffic amongst inte...

CHIP BUMP INTERFACE COMPATIBLE WITH DIFFERENT ORIENTATIONS AND TYPE...

SYSTEM-ON-CHIP HAVING MULTIPLE CIRCUITS AND MEMORY CONTROLLER IN SE...

NETWORK-ON-CHIP ARCHITECTURE FOR HANDLING DIFFERENT DATA SIZES

EFFICIENCY AND QUALITY OF SERVICE IMPROVEMENTS FOR SYSTEMS WITH HIG...

FLEXIBLE QUEUE PROVISIONING FOR PARTITIONED ACCELERATION DEVICE

ADAPTIVE INTEGRATED PROGRAMMABLE DEVICE PLATFORM

ADAPTIVE CHIP-TO-CHIP INTERFACE PROTOCOL ARCHITECTURE

ADAPTIVE ACCELERATION OF TRANSPORT LAYER SECURITY

SYNCHRONIZATION OF SYSTEM RESOURCES IN A MULTI-SOCKET DATA PROCESSI...

MULTI-USE CHIP-TO-CHIP INTERFACE

DATA BUS INVERSION USING MULTIPLE TRANSFORMS

ON-DEMAND PACKETIZATION FOR A CHIP-TO-CHIP INTERFACE

DYNAMICALLY ALLOCATED BUFFER POOLING

LOCALIZED NOC SWITCHING INTERCONNECT FOR HIGH BANDWIDTH INTERFACES

CONFIGURABLE NETWORK-ON-CHIP FOR A PROGRAMMABLE DEVICE

SUBSYSTEM FOR CONFIGURATION, SECURITY, AND MANAGEMENT OF AN ADAPTIV...

PERIPHERAL I/O DEVICE WITH ASSIGNABLE I/O AND COHERENT DOMAINS

CONFIGURABLE NETWORK-ON-CHIP FOR A PROGRAMMABLE DEVICE

HARDWARE-BASED VIRTUAL-TO-PHYSICAL ADDRESS TRANSLATION FOR PROGRAMM...

MEMORY SUBSYSTEM FOR SYSTEM-ON-CHIP