Saikat Bandyopadhyay

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hierarchical access simulation for signaling with more than two sta...
- Patent number 11,543,452
- Issue date Jan 3, 2023
- Xilinx, Inc.
- Saikat Bandyopadhyay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallelizing simulation and hardware co-simulation of circuit desi...
- Patent number 11,475,199
- Issue date Oct 18, 2022
- Xilinx, Inc.
- Saikat Bandyopadhyay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation using accelerated models
- Patent number 11,443,088
- Issue date Sep 13, 2022
- Xilinx, Inc.
- Gaurav Kumar Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Range computation of bitwise operators
- Patent number 11,003,818
- Issue date May 11, 2021
- Xilinx, Inc.
- Ashish Kumar Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Operator aware finite state machine for circuit design simulation
- Patent number 10,726,182
- Issue date Jul 28, 2020
- Xilinx, Inc.
- Sandeep S. Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Framework for reusing cores in simulation
- Patent number 10,671,785
- Issue date Jun 2, 2020
- Xilinx, Inc.
- Valeria Mihalache
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduling events in hardware design language simulation
- Patent number 10,437,949
- Issue date Oct 8, 2019
- Xilinx, Inc.
- Valeria Mihalache
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ADAPTABLE FRAMEWORK FOR CIRCUIT DESIGN SIMULATION VERIFICATION
- Publication number 20240232482
- Publication date Jul 11, 2024
- Xilinx, Inc.
- Saikat Bandyopadhyay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTABLE FRAMEWORK FOR CIRCUIT DESIGN SIMULATION VERIFICATION
- Publication number 20240135074
- Publication date Apr 25, 2024
- Xilinx, Inc.
- Saikat Bandyopadhyay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAVEFORM STIMULUS GENERATION
- Publication number 20240012973
- Publication date Jan 11, 2024
- Xilinx, Inc.
- Sandeep S. Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTBENCH FOR SUB-DESIGN VERIFICATION
- Publication number 20230252212
- Publication date Aug 10, 2023
- Xilinx, Inc.
- Rajvinder S. Klair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR INTERFACING A TESTBENCH TO CIRCUIT SIMULATION
- Publication number 20230169226
- Publication date Jun 1, 2023
- Xilinx, Inc.
- Saikat Bandyopadhyay
- G06 - COMPUTING CALCULATING COUNTING

Saikat Bandyopadhyay

Person

Patents Grantslast 30 patents

Hierarchical access simulation for signaling with more than two sta...

Parallelizing simulation and hardware co-simulation of circuit desi...

Simulation using accelerated models

Range computation of bitwise operators

Operator aware finite state machine for circuit design simulation

Framework for reusing cores in simulation

Scheduling events in hardware design language simulation

Patents Applicationslast 30 patents

ADAPTABLE FRAMEWORK FOR CIRCUIT DESIGN SIMULATION VERIFICATION

ADAPTABLE FRAMEWORK FOR CIRCUIT DESIGN SIMULATION VERIFICATION

WAVEFORM STIMULUS GENERATION

TESTBENCH FOR SUB-DESIGN VERIFICATION

METHOD AND SYSTEM FOR INTERFACING A TESTBENCH TO CIRCUIT SIMULATION