Sailendra Chadalavda

Follow

Person

Milpitas, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Independent test partition clock coordination across multiple test...
- Patent number 10,444,280
- Issue date Oct 15, 2019
- NVIDIA Corporation
- Dheepakkumaran Jayaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan system interface (SSI) module
- Patent number 10,317,463
- Issue date Jun 11, 2019
- NVIDIA Corporation
- Milind Sonawane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test partition external input/output interface control for test par...
- Patent number 10,281,524
- Issue date May 7, 2019
- NVIDIA Corporation
- Sailendra Chadalavda
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TEST PARTITION EXTERNAL INPUT/OUTPUT INTERFACE CONTROL
- Publication number 20170115338
- Publication date Apr 27, 2017
- Sailendra Chadalavda
- G01 - MEASURING TESTING
Information Patent Application
SCAN SYSTEM INTERFACE (SSI) MODULE
- Publication number 20170115346
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR DYNAMIC STANDARD TEST ACCESS (DSTA) FOR A LOG...
- Publication number 20170115345
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Application
INDEPENDENT TEST PARTITION CLOCK COORDINATION ACROSS MULTIPLE TEST...
- Publication number 20170115352
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Dheepakkumaran Jayaraman
- G01 - MEASURING TESTING