Saket K. Goyal

Person

San Ramon, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Core wrapping in the presence of an embedded wrapped core
- Patent number 8,694,951
- Issue date Apr 8, 2014
- LSI Corporation
- Narendra B. Devta Prasanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing a circuit with compressed scan chain subsets
- Patent number 7,831,876
- Issue date Nov 9, 2010
- LSI Corporation
- Saket K. Goyal
- G01 - MEASURING TESTING
Information Patent Grant
Method for creating a JTAG tap controller in a slice for use during...
- Patent number 7,360,133
- Issue date Apr 15, 2008
- LSI Logic Corporation
- Saket Goyal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extensible IO testing implementation
- Patent number 7,284,211
- Issue date Oct 16, 2007
- LSI Corporation
- Saket K. Goyal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling of unused coreware with embedded boundary scan chains to a...
- Patent number 7,188,330
- Issue date Mar 6, 2007
- LSI Logic Corporation
- Saket Goyal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system of generic implementation of sharing test pins wi...
- Patent number 7,181,359
- Issue date Feb 20, 2007
- LSI Logic Corporation
- Saket K. Goyal
- G01 - MEASURING TESTING
Information Patent Grant
Flexible and extensible implementation of sharing test pins in ASIC
- Patent number 7,047,470
- Issue date May 16, 2006
- LSI Logic Corporation
- Saket K. Goyal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed delay prediction of multi-million gate deep sub-micron...
- Patent number 7,006,962
- Issue date Feb 28, 2006
- LSI Logic Corporation
- Saket Goyal
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CORE WRAPPING IN THE PRESENCE OF AN EMBEDDED WRAPPED CORE
- Publication number 20140096097
- Publication date Apr 3, 2014
- LSI Corporation
- Narendra B. Devta Prasanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRICALLY PROGRAMMABLE FUSE CONTROLLER FOR INTEGRATED CIRCUIT ID...
- Publication number 20110279171
- Publication date Nov 17, 2011
- LSI Corporation
- Lihui Cao
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING A CIRCUIT WITH COMPRESSED SCAN CHAIN SUBSETS
- Publication number 20090106613
- Publication date Apr 23, 2009
- LSI Corporation
- Saket K. Goyal
- G01 - MEASURING TESTING
Information Patent Application
Method and system of generic implementation of sharing test pins wi...
- Publication number 20060106563
- Publication date May 18, 2006
- Saket K. Goyal
- G01 - MEASURING TESTING
Information Patent Application
Handling of unused coreware with embedded boundary scan chains to a...
- Publication number 20050262465
- Publication date Nov 24, 2005
- Saket Goyal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for creating a JTAG tap controller in a slice for use during...
- Publication number 20050262460
- Publication date Nov 24, 2005
- Saket Goyal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Extensible IO testing implementation
- Publication number 20040221197
- Publication date Nov 4, 2004
- Saket K. Goyal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flexible and extensible implementation of sharing test pins in ASIC
- Publication number 20040210806
- Publication date Oct 21, 2004
- Saket K. Goyal
- G06 - COMPUTING CALCULATING COUNTING

Saket K. Goyal

Person

Patents Grantslast 30 patents

Core wrapping in the presence of an embedded wrapped core

Testing a circuit with compressed scan chain subsets

Method for creating a JTAG tap controller in a slice for use during...

Extensible IO testing implementation

Handling of unused coreware with embedded boundary scan chains to a...

Method and system of generic implementation of sharing test pins wi...

Flexible and extensible implementation of sharing test pins in ASIC

Distributed delay prediction of multi-million gate deep sub-micron...

Patents Applicationslast 30 patents

CORE WRAPPING IN THE PRESENCE OF AN EMBEDDED WRAPPED CORE

ELECTRICALLY PROGRAMMABLE FUSE CONTROLLER FOR INTEGRATED CIRCUIT ID...

TESTING A CIRCUIT WITH COMPRESSED SCAN CHAIN SUBSETS

Method and system of generic implementation of sharing test pins wi...

Handling of unused coreware with embedded boundary scan chains to a...

Method for creating a JTAG tap controller in a slice for use during...

Extensible IO testing implementation

Flexible and extensible implementation of sharing test pins in ASIC