Salil R. Raje

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Creating a standard cell circuit design from a programmable logic d...
- Patent number 8,667,437
- Issue date Mar 4, 2014
- Xilinx, Inc.
- Salil Ravindra Raje
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioning a large design across multiple devices
- Patent number 7,873,927
- Issue date Jan 18, 2011
- Xilinx, Inc.
- David A. Knol
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic pin placement for integrated circuits to aid circuit boar...
- Patent number 7,594,212
- Issue date Sep 22, 2009
- Xilinx, Inc.
- Dinesh D. Gaitonde
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Strategies for generating an implementation of an electronic design
- Patent number 7,519,938
- Issue date Apr 14, 2009
- Xilinx, Inc.
- Robert E. Shortt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of memory and run-time efficient hierarchical timing analysi...
- Patent number 7,437,695
- Issue date Oct 14, 2008
- Xilinx, Inc.
- Abhishek Ranjan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for representing the logical and physical information of an...
- Patent number 7,418,686
- Issue date Aug 26, 2008
- Xilinx, Inc.
- David A. Knol
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioning a large design across multiple devices
- Patent number 7,370,302
- Issue date May 6, 2008
- Xilinx, Inc.
- David A. Knol
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data structures for representing the logical and physical informati...
- Patent number 7,146,595
- Issue date Dec 5, 2006
- Xilinx, Inc.
- David A. Knol
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process for adjusting data structures of a floorplan upon changes o...
- Patent number 7,120,892
- Issue date Oct 10, 2006
- Xilinx, Inc.
- David A. Knol
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for creating a physical hierarchy of a chip without restrict...
- Patent number 7,117,473
- Issue date Oct 3, 2006
- Xilinx, Inc.
- David A. Knol
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for representing the logical and physical information of an...
- Patent number 7,073,149
- Issue date Jul 4, 2006
- Xilinx, Inc.
- David A. Knol
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement method for integrated circuit design using topo-clustering
- Patent number 6,961,916
- Issue date Nov 1, 2005
- Synopsys, Inc.
- Majid Sarrafzadeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement method for integrated circuit design using topo-clustering
- Patent number 6,851,099
- Issue date Feb 1, 2005
- Synopsys, Inc.
- Majid Sarrafzadeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating sign-off prototypes for the des...
- Patent number 6,775,808
- Issue date Aug 10, 2004
- Monterey Design Systems, Inc.
- Salil R. Raje
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for progressive clock tree or mesh construction c...
- Patent number 6,651,232
- Issue date Nov 18, 2003
- Monterey Design Systems, Inc.
- Lawrence Pileggi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to optimize net lists using simultaneous placement and logic...
- Patent number 6,523,161
- Issue date Feb 18, 2003
- Monterey Design Systems, Inc.
- Padmini Gopalakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement method for integrated circuit design using topo-clustering
- Patent number 6,442,743
- Issue date Aug 27, 2002
- Monterey Design Systems
- Majid Sarrafzadeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for design optimization using logical and physical information
- Patent number 6,286,128
- Issue date Sep 4, 2001
- Monterey Design Systems, Inc.
- Lawrence Pileggi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CREATING A STANDARD CELL CIRCUIT DESIGN FROM A PROGRAMMABLE LOGIC D...
- Publication number 20090235222
- Publication date Sep 17, 2009
- Xilinx, Inc.
- Salil Ravindra Raje
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data structures for representing the logical and physical informati...
- Publication number 20050204315
- Publication date Sep 15, 2005
- David A. Knol
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System for representing the logical and physical information of an...
- Publication number 20050198605
- Publication date Sep 8, 2005
- David A. Knol
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Placement method for integrated circuit design using topo-clustering
- Publication number 20020138816
- Publication date Sep 26, 2002
- Majid Sarrafzadeh
- G06 - COMPUTING CALCULATING COUNTING

Salil R. Raje

Person

Patents Grantslast 30 patents

Creating a standard cell circuit design from a programmable logic d...

Partitioning a large design across multiple devices

Automatic pin placement for integrated circuits to aid circuit boar...

Strategies for generating an implementation of an electronic design

Method of memory and run-time efficient hierarchical timing analysi...

System for representing the logical and physical information of an...

Partitioning a large design across multiple devices

Data structures for representing the logical and physical informati...

Process for adjusting data structures of a floorplan upon changes o...

System for creating a physical hierarchy of a chip without restrict...

System for representing the logical and physical information of an...

Placement method for integrated circuit design using topo-clustering

Placement method for integrated circuit design using topo-clustering

Method and apparatus for generating sign-off prototypes for the des...

Method and system for progressive clock tree or mesh construction c...

Method to optimize net lists using simultaneous placement and logic...

Placement method for integrated circuit design using topo-clustering

Method for design optimization using logical and physical information

Patents Applicationslast 30 patents

CREATING A STANDARD CELL CIRCUIT DESIGN FROM A PROGRAMMABLE LOGIC D...

Data structures for representing the logical and physical informati...

System for representing the logical and physical information of an...

Placement method for integrated circuit design using topo-clustering