Salvador Palanca

Person

Gold River, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
MFENCE and LFENCE micro-architectural implementation method and system
- Patent number 9,612,835
- Issue date Apr 4, 2017
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MFENCE and LFENCE micro-architectural implementation method and system
- Patent number 9,383,998
- Issue date Jul 5, 2016
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MFENCE and LFENCE micro-architectural implementation method and system
- Patent number 9,342,310
- Issue date May 17, 2016
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MFENCE and LFENCE micro-architectural implementation method and system
- Patent number 9,098,268
- Issue date Aug 4, 2015
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MFENCE and LFENCE micro-architectural implementation method and system
- Patent number 8,959,314
- Issue date Feb 17, 2015
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for accessing memory in parallel computing using...
- Patent number 8,171,261
- Issue date May 1, 2012
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power cache architecture
- Patent number 7,136,984
- Issue date Nov 14, 2006
- Intel Corporation
- Subramaniam J. Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for cache replacement for a multiple variable-...
- Patent number 6,889,291
- Issue date May 3, 2005
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Opportunistic sharing of graphics resources to enhance CPU performa...
- Patent number 6,842,180
- Issue date Jan 11, 2005
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for cache sharing
- Patent number 6,801,208
- Issue date Oct 5, 2004
- Intel Corporation
- Jagganath Keshava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized configurable scheme for demand based resource sharing of...
- Patent number 6,782,455
- Issue date Aug 24, 2004
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for cache replacement for a multiple variable-...
- Patent number 6,772,291
- Issue date Aug 3, 2004
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically configurable clocking scheme for demand based resource...
- Patent number 6,735,712
- Issue date May 11, 2004
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MFENCE and LFENCE micro-architectural implementation method and system
- Patent number 6,678,810
- Issue date Jan 13, 2004
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache dynamically configured for simultaneous accesses by multiple...
- Patent number 6,665,775
- Issue date Dec 16, 2003
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MFENCE and LFENCE micro-architectural implementation method and system
- Patent number 6,651,151
- Issue date Nov 18, 2003
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for prefetching data into cache
- Patent number 6,643,745
- Issue date Nov 4, 2003
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared cache structure for temporal and non-temporal instructions
- Patent number 6,584,547
- Issue date Jun 24, 2003
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CLFLUSH micro-architectural implementation method and system
- Patent number 6,546,462
- Issue date Apr 8, 2003
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for load buffers
- Patent number 6,526,499
- Issue date Feb 25, 2003
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast invalidation scheme for caches
- Patent number 6,438,658
- Issue date Aug 20, 2002
- Intel Corporation
- Harikrishna B. Baliga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized configurable scheme for demand based resource sharing of...
- Patent number 6,434,673
- Issue date Aug 13, 2002
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing non-temporal loads
- Patent number 6,223,258
- Issue date Apr 24, 2001
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for senior loads
- Patent number 6,216,215
- Issue date Apr 10, 2001
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing non-temporal stores
- Patent number 6,205,520
- Issue date Mar 20, 2001
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared cache structure for temporal and non-temporal information us...
- Patent number 6,202,129
- Issue date Mar 13, 2001
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for writing select non-contiguous bytes of data with single...
- Patent number 6,173,393
- Issue date Jan 9, 2001
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for optimizing write combining performance in a s...
- Patent number 6,122,715
- Issue date Sep 19, 2000
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronization of weakly ordered write combining operations using...
- Patent number 6,073,210
- Issue date Jun 6, 2000
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM
- Publication number 20170206088
- Publication date Jul 20, 2017
- lntel Corporation
- Stephen A. Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MFENCE and LFENCE Micro-Architectural Implementation Method and System
- Publication number 20130305018
- Publication date Nov 14, 2013
- SALVADOR PALANCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM
- Publication number 20130205117
- Publication date Aug 8, 2013
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM
- Publication number 20130073834
- Publication date Mar 21, 2013
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM
- Publication number 20130067200
- Publication date Mar 14, 2013
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MFENCE and LFENCE Micro-Architectural Implementation Method and System
- Publication number 20120191951
- Publication date Jul 26, 2012
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low power cache architecture
- Publication number 20050097277
- Publication date May 5, 2005
- Subramaniam J. Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamically configurable clocking scheme for demand based resource...
- Publication number 20040123176
- Publication date Jun 24, 2004
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MFENCE and LFENCE micro-architectural implementation method and system
- Publication number 20040044883
- Publication date Mar 4, 2004
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MFENCE and LFENCE micro-architectural implementation method and system
- Publication number 20030084259
- Publication date May 1, 2003
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for cache replacement for a multiple variable-...
- Publication number 20030023827
- Publication date Jan 30, 2003
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimized configurable scheme for demand based resource sharing of...
- Publication number 20020178334
- Publication date Nov 28, 2002
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for cache sharing
- Publication number 20020116576
- Publication date Aug 22, 2002
- Jagannath Keshava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Shared cache structure for temporal and non-temporal instructions
- Publication number 20020007441
- Publication date Jan 17, 2002
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for senior loads
- Publication number 20010001153
- Publication date May 10, 2001
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING

Salvador Palanca

Person

Patents Grantslast 30 patents

MFENCE and LFENCE micro-architectural implementation method and system

MFENCE and LFENCE micro-architectural implementation method and system

MFENCE and LFENCE micro-architectural implementation method and system

MFENCE and LFENCE micro-architectural implementation method and system

MFENCE and LFENCE micro-architectural implementation method and system

Method and system for accessing memory in parallel computing using...

Low power cache architecture

Method and apparatus for cache replacement for a multiple variable-...

Opportunistic sharing of graphics resources to enhance CPU performa...

System and method for cache sharing

Optimized configurable scheme for demand based resource sharing of...

Method and apparatus for cache replacement for a multiple variable-...

Dynamically configurable clocking scheme for demand based resource...

MFENCE and LFENCE micro-architectural implementation method and system

Cache dynamically configured for simultaneous accesses by multiple...

MFENCE and LFENCE micro-architectural implementation method and system

Method and apparatus for prefetching data into cache

Shared cache structure for temporal and non-temporal instructions

CLFLUSH micro-architectural implementation method and system

Method and apparatus for load buffers

Fast invalidation scheme for caches

Optimized configurable scheme for demand based resource sharing of...

Method and apparatus for implementing non-temporal loads

Method and apparatus for senior loads

Method and apparatus for implementing non-temporal stores

Shared cache structure for temporal and non-temporal information us...

System for writing select non-contiguous bytes of data with single...

Method and system for optimizing write combining performance in a s...

Synchronization of weakly ordered write combining operations using...

Patents Applicationslast 30 patents

MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM

MFENCE and LFENCE Micro-Architectural Implementation Method and System

MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM

MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM

MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM

MFENCE and LFENCE Micro-Architectural Implementation Method and System

Low power cache architecture

Dynamically configurable clocking scheme for demand based resource...

MFENCE and LFENCE micro-architectural implementation method and system

MFENCE and LFENCE micro-architectural implementation method and system

Method and apparatus for cache replacement for a multiple variable-...

Optimized configurable scheme for demand based resource sharing of...

System and method for cache sharing

Shared cache structure for temporal and non-temporal instructions

Method and apparatus for senior loads