San Wong

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Empirical prediction of simultaneous switching noise
- Patent number 8,504,976
- Issue date Aug 6, 2013
- Altera Corporation
- Zhuyuan Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Empirical prediction of simultaneous switching noise
- Patent number 8,214,781
- Issue date Jul 3, 2012
- Altera Corporation
- Zhuyuan Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Jitter estimation in phase-locked loops
- Patent number 8,170,823
- Issue date May 1, 2012
- Altera Corporation
- Daniel Tun Lai Chow
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Transceiver link bit error rate prediction
- Patent number 8,103,469
- Issue date Jan 24, 2012
- Altera Corporation
- San Wong
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for improving data transfer
- Patent number 8,041,983
- Issue date Oct 18, 2011
- Altera Corporation
- San Wong
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for analyzing input/output simultaneous switching...
- Patent number 8,001,508
- Issue date Aug 16, 2011
- Altera Corporation
- Nafira Daud
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Jitter estimation in phase-locked loops
- Patent number 7,890,279
- Issue date Feb 15, 2011
- Altera Corporation
- Daniel Tun Lai Chow
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for hardware timing optimizer
- Patent number 7,437,591
- Issue date Oct 14, 2008
- Altera Corporation
- San Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit error rate tester implemented in a programmable logic device
- Patent number 7,194,666
- Issue date Mar 20, 2007
- Altera Corporation
- San Wong
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
EMPIRICAL PREDICTION OF SIMULTANEOUS SWITCHING NOISE
- Publication number 20120239338
- Publication date Sep 20, 2012
- Zhuyuan Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR HARDWARE TIMING OPTIMIZER
- Publication number 20090019304
- Publication date Jan 15, 2009
- San Wong
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Empirical prediction of simultaneous switching noise

Empirical prediction of simultaneous switching noise

Jitter estimation in phase-locked loops

Transceiver link bit error rate prediction

Method and apparatus for improving data transfer

Method and system for analyzing input/output simultaneous switching...

Jitter estimation in phase-locked loops

Method and apparatus for hardware timing optimizer

Bit error rate tester implemented in a programmable logic device

Patents Applicationslast 30 patents

EMPIRICAL PREDICTION OF SIMULTANEOUS SWITCHING NOISE

METHOD AND APPARATUS FOR HARDWARE TIMING OPTIMIZER