Sandeep Bhatia

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and mechanism for implementing electronic designs having pow...
- Patent number RE44479
- Issue date Sep 3, 2013
- Cadence Design Systems, Inc.
- Qi Wang
- 716 - Computer-aided design and analysis of circuits and semiconductor masks
Information Patent Grant
Method and mechanism for implementing electronic designs having pow...
- Patent number 8,516,422
- Issue date Aug 20, 2013
- Cadence Design Systems, Inc.
- Qi Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for scan testing of integrated circuits with scan registers
- Patent number 8,078,925
- Issue date Dec 13, 2011
- Cadence Design Systems, Inc.
- Sandeep Bhatia
- G01 - MEASURING TESTING
Information Patent Grant
Scan testing architectures for power-shutoff aware systems
- Patent number 8,001,433
- Issue date Aug 16, 2011
- Cadence Design Systems, Inc.
- Sandeep Bhatia
- G01 - MEASURING TESTING
Information Patent Grant
Test compaction using linear-matrix driven scan chains
- Patent number 7,925,941
- Issue date Apr 12, 2011
- Cadence Design Systems, Inc.
- Sandeep Bhatia
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus for scan testing of integrated circuits with...
- Patent number 7,743,298
- Issue date Jun 22, 2010
- Cadence Design Systems, Inc.
- Sandeep Bhatia
- G01 - MEASURING TESTING
Information Patent Grant
Method and mechanism for implementing electronic designs having pow...
- Patent number 7,739,629
- Issue date Jun 15, 2010
- Cadence Design Systems, Inc.
- Qi Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power scan test for integrated circuits
- Patent number 7,693,676
- Issue date Apr 6, 2010
- Cadence Design Systems, Inc.
- Brion L. Keller
- G01 - MEASURING TESTING
Information Patent Grant
Dual scan chain design method and apparatus
- Patent number 7,657,809
- Issue date Feb 2, 2010
- Cadence Design Systems, Inc.
- Sandeep Bhatia
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for clock skew independent scan register chains
- Patent number 7,613,969
- Issue date Nov 3, 2009
- Cadence Design Systems, Inc.
- Sandeep Bhatia
- G01 - MEASURING TESTING
Information Patent Grant
Test compaction using linear-matrix driven scan chains
- Patent number 7,584,392
- Issue date Sep 1, 2009
- Cadence Design Systems, Inc.
- Sandeep Bhatia
- G01 - MEASURING TESTING
Information Patent Grant
Scan register and methods of using the same
- Patent number 7,457,998
- Issue date Nov 25, 2008
- Cadence Design Systems, Inc.
- Sandeep Bhatia
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
TEST COMPACTION USING LINEAR-MATRIX DRIVEN SCAN CHAINS
- Publication number 20100058129
- Publication date Mar 4, 2010
- Cadence Design Systems, Inc.
- Sandeep Bhatia
- G01 - MEASURING TESTING
Information Patent Application
Method and mechanism for implementing electronic designs having pow...
- Publication number 20070245285
- Publication date Oct 18, 2007
- Qi Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for clock skew independent scan register chains
- Publication number 20060095819
- Publication date May 4, 2006
- Cadence Design Systems, Inc.
- Sandeep Bhatia
- G01 - MEASURING TESTING
Information Patent Application
Test compaction using linear-matrix driven scan chains
- Publication number 20040237014
- Publication date Nov 25, 2004
- Sandeep Bhatia
- G01 - MEASURING TESTING

Sandeep Bhatia

Person

Patents Grantslast 30 patents

Method and mechanism for implementing electronic designs having pow...

Method and mechanism for implementing electronic designs having pow...

Apparatus for scan testing of integrated circuits with scan registers

Scan testing architectures for power-shutoff aware systems

Test compaction using linear-matrix driven scan chains

Methods and apparatus for scan testing of integrated circuits with...

Method and mechanism for implementing electronic designs having pow...

Low power scan test for integrated circuits

Dual scan chain design method and apparatus

Method and system for clock skew independent scan register chains

Test compaction using linear-matrix driven scan chains

Scan register and methods of using the same

Patents Applicationslast 30 patents

TEST COMPACTION USING LINEAR-MATRIX DRIVEN SCAN CHAINS

Method and mechanism for implementing electronic designs having pow...

Method and system for clock skew independent scan register chains

Test compaction using linear-matrix driven scan chains