Sandeep Bhutani

Person

Towson, MD, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multiple derating factor sets for delay calculation and library gen...
- Patent number 8,539,411
- Issue date Sep 17, 2013
- LSI Corporation
- Qian Cui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and computer program for generating grounded shielding wires...
- Patent number 8,516,425
- Issue date Aug 20, 2013
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for balancing signal delay skew
- Patent number 8,239,813
- Issue date Aug 7, 2012
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Moment computation algorithms in VLSI system
- Patent number 8,156,466
- Issue date Apr 10, 2012
- LSI Corporation
- Weiqing Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal delay skew reduction system
- Patent number 7,996,804
- Issue date Aug 9, 2011
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generation of an extracted timing model file
- Patent number 7,689,965
- Issue date Mar 30, 2010
- LSI Corporation
- Peter Lindberg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Probabilistic noise analysis
- Patent number 7,661,083
- Issue date Feb 9, 2010
- LSI Corporation
- Payman Zarkesh-Ha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification of an extracted timing model file
- Patent number 7,577,928
- Issue date Aug 18, 2009
- LSI Logic Corporation
- Peter Lindberg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing a parasitic graph in moment computation algorithms in VLSI...
- Patent number 7,539,960
- Issue date May 26, 2009
- LSI Corporation
- Weiqing Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Probabilistic noise analysis
- Patent number 7,376,918
- Issue date May 20, 2008
- LSI Corporation
- Payman Zarkesh-Ha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for avoiding false path pessimism in estimating net delay fo...
- Patent number 7,334,204
- Issue date Feb 19, 2008
- LSI Logic Corporation
- Weiqing Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequency dependent timing margin
- Patent number 7,299,435
- Issue date Nov 20, 2007
- LSI Corporation
- Qian Cui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay computation speed up and incrementality
- Patent number 7,260,801
- Issue date Aug 21, 2007
- LSI Corporation
- Sandeep Bhutani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Negative bias temperature instability modeling
- Patent number 7,228,516
- Issue date Jun 5, 2007
- LSI Corporation
- Qian Cui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for reducing a parasitic graph in moment computation in VLSI...
- Patent number 7,082,583
- Issue date Jul 25, 2006
- LSI Logic Corporation
- Weiqing Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of predicting quiescent current variation of an integrated c...
- Patent number 7,069,178
- Issue date Jun 27, 2006
- LSI Logic Corporation
- Qian Cui
- G01 - MEASURING TESTING
Information Patent Grant
Method of estimating a local average crosstalk voltage for a variab...
- Patent number 6,990,420
- Issue date Jan 24, 2006
- LSI Logic Corporation
- Weiqing Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of delay calculation for variation in interconnect metal pro...
- Patent number 6,880,142
- Issue date Apr 12, 2005
- LSI Logic Corporation
- Qian Cui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Driver waveform modeling with multiple effective capacitances
- Patent number 6,845,348
- Issue date Jan 18, 2005
- LSI Logic Corporation
- Prasad Subbarao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
4 point derating scheme for propagation delay and setup/hold time c...
- Patent number 6,820,048
- Issue date Nov 16, 2004
- LSI Logic Corporation
- Sandeep Bhutani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modeling delays for small nets in an integrated circuit design
- Patent number 6,587,999
- Issue date Jul 1, 2003
- LSI Logic Corporation
- Lei Chen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SIGNAL DELAY SKEW REDUCTION SYSTEM
- Publication number 20120278783
- Publication date Nov 1, 2012
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL DELAY SKEW REDUCTION SYSTEM
- Publication number 20110258587
- Publication date Oct 20, 2011
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple derating factor sets for delay calculation and library gen...
- Publication number 20090217226
- Publication date Aug 27, 2009
- Qian Cui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL DELAY SKEW REDUCTION SYSTEM
- Publication number 20090187873
- Publication date Jul 23, 2009
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MOMENT COMPUTATION ALGORITHMS IN VLSI SYSTEM
- Publication number 20090158228
- Publication date Jun 18, 2009
- LSI Corporation
- Weiqing Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROBABILISTIC NOISE ANALYSIS
- Publication number 20080163145
- Publication date Jul 3, 2008
- LSI Corporation
- Payman Zarkesh-Ha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Verification of an extracted timing model file
- Publication number 20070220462
- Publication date Sep 20, 2007
- LSI Logic Corporation
- Peter Lindberg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generation of an extracted timing model file
- Publication number 20070186198
- Publication date Aug 9, 2007
- LSI Logic Corporation
- Peter Lindberg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System for avoiding false path pessimism in estimating net delay fo...
- Publication number 20070157143
- Publication date Jul 5, 2007
- Weiqing Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay computation speed up and incrementality
- Publication number 20070028199
- Publication date Feb 1, 2007
- Sandeep Bhutani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MOMENT COMPUTATION ALGORITHMS IN VLSI SYSTEM
- Publication number 20060253811
- Publication date Nov 9, 2006
- LSI Logic Corporation
- WEIQING GUO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Probabilistic noise analysis
- Publication number 20060206843
- Publication date Sep 14, 2006
- Payman Zarkesh-Ha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Frequency dependent timing margin
- Publication number 20060190879
- Publication date Aug 24, 2006
- Qian Cui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Negative bias temperature instability modeling
- Publication number 20060190859
- Publication date Aug 24, 2006
- Qian Cui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of predicting quiescent current variation of an integrated c...
- Publication number 20060074589
- Publication date Apr 6, 2006
- Qian Cui
- G01 - MEASURING TESTING
Information Patent Application
Method of estimating a local average crosstalk voltage for a variab...
- Publication number 20050251354
- Publication date Nov 10, 2005
- Weiqing Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Monent computation algorithms in VLSI system
- Publication number 20040098677
- Publication date May 20, 2004
- Weiqing Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of delay calculation for variation in interconnect metal pro...
- Publication number 20040078765
- Publication date Apr 22, 2004
- Qian Cui
- G06 - COMPUTING CALCULATING COUNTING

Sandeep Bhutani

Person

Patents Grantslast 30 patents

Multiple derating factor sets for delay calculation and library gen...

Method and computer program for generating grounded shielding wires...

Method and apparatus for balancing signal delay skew

Moment computation algorithms in VLSI system

Signal delay skew reduction system

Generation of an extracted timing model file

Probabilistic noise analysis

Verification of an extracted timing model file

Reducing a parasitic graph in moment computation algorithms in VLSI...

Probabilistic noise analysis

System for avoiding false path pessimism in estimating net delay fo...

Frequency dependent timing margin

Delay computation speed up and incrementality

Negative bias temperature instability modeling

Method for reducing a parasitic graph in moment computation in VLSI...

Method of predicting quiescent current variation of an integrated c...

Method of estimating a local average crosstalk voltage for a variab...

Method of delay calculation for variation in interconnect metal pro...

Driver waveform modeling with multiple effective capacitances

4 point derating scheme for propagation delay and setup/hold time c...

Modeling delays for small nets in an integrated circuit design

Patents Applicationslast 30 patents

SIGNAL DELAY SKEW REDUCTION SYSTEM

SIGNAL DELAY SKEW REDUCTION SYSTEM

Multiple derating factor sets for delay calculation and library gen...

SIGNAL DELAY SKEW REDUCTION SYSTEM

MOMENT COMPUTATION ALGORITHMS IN VLSI SYSTEM

PROBABILISTIC NOISE ANALYSIS

Verification of an extracted timing model file

Generation of an extracted timing model file

System for avoiding false path pessimism in estimating net delay fo...

Delay computation speed up and incrementality

MOMENT COMPUTATION ALGORITHMS IN VLSI SYSTEM

Probabilistic noise analysis

Frequency dependent timing margin

Negative bias temperature instability modeling

Method of predicting quiescent current variation of an integrated c...

Method of estimating a local average crosstalk voltage for a variab...

Monent computation algorithms in VLSI system

Method of delay calculation for variation in interconnect metal pro...