Sandeep Jain

Person

Rewari, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Scan compression through pin data encoding
- Patent number 12,105,145
- Issue date Oct 1, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Redundancy circuit
- Patent number 11,848,672
- Issue date Dec 19, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scan compression through pin data encoding
- Patent number 11,782,092
- Issue date Oct 10, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
System for facilitating secure communication in system-on-chips
- Patent number 11,768,987
- Issue date Sep 26, 2023
- NXP USA, INC.
- Sandeep Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for securely patching read-only-memory code
- Patent number 11,328,066
- Issue date May 10, 2022
- NXP USA, INC.
- Atul Dahiya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Side channel attack protection
- Patent number 11,244,078
- Issue date Feb 8, 2022
- NXP USA, INC.
- Stefan Doll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Side channel attack protection
- Patent number 11,106,830
- Issue date Aug 31, 2021
- NXP USA, INC.
- Stefan Doll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Idle loop detection and control for processors
- Patent number 10,963,036
- Issue date Mar 30, 2021
- NXP USA, INC.
- Ashish Mathur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of scan reset upon entering scan mode
- Patent number 10,955,473
- Issue date Mar 23, 2021
- NXP B.V.
- Sandeep Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware and software debug using data dependency tracing
- Patent number 10,474,552
- Issue date Nov 12, 2019
- NXP USA, INC.
- Sandeep Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault attack protection against synchronized fault injections
- Patent number 10,305,479
- Issue date May 28, 2019
- NXP B.V.
- Stefan Doll
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Watchpoint support system for functional simulator
- Patent number 9,176,821
- Issue date Nov 3, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Sandeep Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-threaded system for performing atomic binary translations
- Patent number 9,053,035
- Issue date Jun 9, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Ashish Mathur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for debugging scan chains
- Patent number 8,458,541
- Issue date Jun 4, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Sequential scan based techniques to test interface between modules...
- Patent number 7,421,634
- Issue date Sep 2, 2008
- Texas Instruments Incorporated
- Naga Satya Srikanth Puvvada
- G01 - MEASURING TESTING
Information Patent Grant
Scan tests tolerant to indeterminate states when employing signatur...
- Patent number 7,404,126
- Issue date Jul 22, 2008
- Texas Instruments Incorporated
- Sandeep Jain
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
COMPRESSION-BASED SCAN TEST SYSTEM
- Publication number 20240393393
- Publication date Nov 28, 2024
- STMicroelectronics International N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Application
CLUSTERING CLOCK CHAIN DATA FOR TEST-TIME REDUCTION
- Publication number 20240385241
- Publication date Nov 21, 2024
- STMicroelectronics International N.V.
- Sandeep JAIN
- G01 - MEASURING TESTING
Information Patent Application
SCAN COMPRESSION THROUGH PIN DATA ENCODING
- Publication number 20230375617
- Publication date Nov 23, 2023
- STMicroelectronics International N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Application
REDUNDANCY CIRCUIT
- Publication number 20230327674
- Publication date Oct 12, 2023
- STMicroelectronics International N.V.
- Sandeep Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND SYSTEM FOR SECURELY PATCHING READ-ONLY-MEMORY CODE
- Publication number 20210319107
- Publication date Oct 14, 2021
- NXP USA, Inc.
- Atul Dahiya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM FOR FACILITATING SECURE COMMUNICATION IN SYSTEM-ON-CHIPS
- Publication number 20210312115
- Publication date Oct 7, 2021
- NXP USA, Inc.
- Sandeep Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-PROVISIONING AND PROTECTION OF A SECRET KEY
- Publication number 20200195432
- Publication date Jun 18, 2020
- NXP USA, Inc.
- Stefan Doll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIDE CHANNEL ATTACK PROTECTION
- Publication number 20200184113
- Publication date Jun 11, 2020
- NXP USA, Inc.
- Stefan Doll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Idle Loop Detection And Control For Processors
- Publication number 20190317589
- Publication date Oct 17, 2019
- NXP USA, Inc.
- Ashish Mathur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE AND SOFTWARE DEBUG USING DATA DEPENDENCY TRACING
- Publication number 20180336080
- Publication date Nov 22, 2018
- NXP USA, Inc.
- Sandeep Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-THREADED SYSTEM FOR PERFORMING ATOMIC BINARY TRANSLATIONS
- Publication number 20150149725
- Publication date May 28, 2015
- Ashish Mathur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WATCHPOINT SUPPORT SYSTEM FOR FUNCTIONAL SIMULATOR
- Publication number 20150121127
- Publication date Apr 30, 2015
- Sandeep Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR DEBUGGING SCAN CHAINS
- Publication number 20120246531
- Publication date Sep 27, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR SCAN TESTING INTEGRATED CIRCUITS
- Publication number 20120137187
- Publication date May 31, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Application
Scan Tests Tolerant to Indeterminate States When Employing Signatur...
- Publication number 20070234150
- Publication date Oct 4, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Application
Sequential Scan Based Techniques to Test Interface Between Modules...
- Publication number 20060248422
- Publication date Nov 2, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Naga Satya Srikanth Puvvada
- G01 - MEASURING TESTING

Sandeep Jain

Person

Patents Grantslast 30 patents

Scan compression through pin data encoding

Redundancy circuit

Scan compression through pin data encoding

System for facilitating secure communication in system-on-chips

Method and system for securely patching read-only-memory code

Side channel attack protection

Side channel attack protection

Idle loop detection and control for processors

System and method of scan reset upon entering scan mode

Hardware and software debug using data dependency tracing

Fault attack protection against synchronized fault injections

Watchpoint support system for functional simulator

Multi-threaded system for performing atomic binary translations

System and method for debugging scan chains

Sequential scan based techniques to test interface between modules...

Scan tests tolerant to indeterminate states when employing signatur...

Patents Applicationslast 30 patents

COMPRESSION-BASED SCAN TEST SYSTEM

CLUSTERING CLOCK CHAIN DATA FOR TEST-TIME REDUCTION

SCAN COMPRESSION THROUGH PIN DATA ENCODING

REDUNDANCY CIRCUIT

METHOD AND SYSTEM FOR SECURELY PATCHING READ-ONLY-MEMORY CODE

SYSTEM FOR FACILITATING SECURE COMMUNICATION IN SYSTEM-ON-CHIPS

SELF-PROVISIONING AND PROTECTION OF A SECRET KEY

SIDE CHANNEL ATTACK PROTECTION

Idle Loop Detection And Control For Processors

HARDWARE AND SOFTWARE DEBUG USING DATA DEPENDENCY TRACING

MULTI-THREADED SYSTEM FOR PERFORMING ATOMIC BINARY TRANSLATIONS

WATCHPOINT SUPPORT SYSTEM FOR FUNCTIONAL SIMULATOR

SYSTEM AND METHOD FOR DEBUGGING SCAN CHAINS

SYSTEM AND METHOD FOR SCAN TESTING INTEGRATED CIRCUITS

Scan Tests Tolerant to Indeterminate States When Employing Signatur...

Sequential Scan Based Techniques to Test Interface Between Modules...