Sandeep Suresh NAVADA

Person

Raleigh, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Error containment for enabling local checkpoint and recovery
- Patent number 11,720,440
- Issue date Aug 8, 2023
- NVIDIA Corporation
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storing narrow produced values for instruction operands directly in...
- Patent number 10,108,417
- Issue date Oct 23, 2018
- QUALCOMM Incorporated
- Anil Krishna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for selective renaming in a microprocessor
- Patent number 9,471,325
- Issue date Oct 18, 2016
- QUALCOMM Incorporated
- Anil Krishna
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Cooperative Group Arrays
- Publication number 20230289215
- Publication date Sep 14, 2023
- NVIDIA Corporation
- Greg PALMER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distributed Shared Memory
- Publication number 20230289189
- Publication date Sep 14, 2023
- NVIDIA Corporation
- Prakash BANGALORE PRABHAKAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTABLE CACHE POLICY
- Publication number 20230236977
- Publication date Jul 27, 2023
- NVIDIA Corporation
- Kapil Dev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CONTAINMENT FOR ENABLING LOCAL CHECKPOINT AND RECOVERY
- Publication number 20230011863
- Publication date Jan 12, 2023
- NVIDIA Corporation
- NAVEEN CHERUKURI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING EARLY PIPELINE OPTIMIZATION OF CONDITIONAL INSTRUCTIONS I...
- Publication number 20190294443
- Publication date Sep 26, 2019
- QUALCOMM Incorporated
- Sandeep Suresh Navada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYPERVECTOR-BASED BRANCH PREDICTION
- Publication number 20170322810
- Publication date Nov 9, 2017
- QUALCOMM Incorporated
- Sandeep Suresh NAVADA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRANCH TARGET INSTRUCTION CACHE (BTIC) TO STORE A CONDITIONAL BRANC...
- Publication number 20170083333
- Publication date Mar 23, 2017
- QUALCOMM Incorporated
- Niket Kumar CHOUDHARY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL REGISTER FILE SYSTEM
- Publication number 20170060593
- Publication date Mar 2, 2017
- QUALCOMM Incorporated
- Anil KRISHNA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORING NARROW PRODUCED VALUES FOR INSTRUCTION OPERANDS DIRECTLY IN...
- Publication number 20170046154
- Publication date Feb 16, 2017
- QUALCOMM Incorporated
- Anil Krishna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHYSICAL REGISTER SCRUBBING IN A COMPUTER MICROPROCESSOR
- Publication number 20150268959
- Publication date Sep 24, 2015
- QUALCOMM Incorporated
- Anil KRISHNA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SELECTIVE RENAMING IN A MICROPROCESSOR
- Publication number 20150019843
- Publication date Jan 15, 2015
- QUALCOMM Incorporated
- Anil KRISHNA
- G06 - COMPUTING CALCULATING COUNTING

Sandeep Suresh NAVADA

Person

Patents Grantslast 30 patents

Error containment for enabling local checkpoint and recovery

Storing narrow produced values for instruction operands directly in...

Method and apparatus for selective renaming in a microprocessor

Patents Applicationslast 30 patents

Cooperative Group Arrays

Distributed Shared Memory

SELECTABLE CACHE POLICY

ERROR CONTAINMENT FOR ENABLING LOCAL CHECKPOINT AND RECOVERY

PROVIDING EARLY PIPELINE OPTIMIZATION OF CONDITIONAL INSTRUCTIONS I...

HYPERVECTOR-BASED BRANCH PREDICTION

BRANCH TARGET INSTRUCTION CACHE (BTIC) TO STORE A CONDITIONAL BRANC...

HIERARCHICAL REGISTER FILE SYSTEM

STORING NARROW PRODUCED VALUES FOR INSTRUCTION OPERANDS DIRECTLY IN...

PHYSICAL REGISTER SCRUBBING IN A COMPUTER MICROPROCESSOR

METHOD AND APPARATUS FOR SELECTIVE RENAMING IN A MICROPROCESSOR