Sandip Das

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Clock gating for system-on-chip elements
- Patent number 10,074,053
- Issue date Sep 11, 2018
- NetSpeed Systems
- Sailesh Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock gating for system-on-chip elements
- Patent number 9,571,341
- Issue date Feb 14, 2017
- NetSpeed Systems
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
CLOCK GATING FOR SYSTEM-ON-CHIP ELEMENTS
- Publication number 20170103332
- Publication date Apr 13, 2017
- NETSPEED SYSTEMS
- Sailesh Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK GATING FOR SYSTEM-ON-CHIP ELEMENTS
- Publication number 20170063618
- Publication date Mar 2, 2017
- NETSPEED SYSTEMS
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE