Sandip Kundu

Person

Mohegan Lake, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method for detecting or repairing minimum delay errors
- Patent number 9,520,877
- Issue date Dec 13, 2016
- Intel Corporation
- Pascal A. Meinerzhagen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Weight compression/decompression system
- Patent number 7,197,721
- Issue date Mar 27, 2007
- Intel Corporation
- Srinivas Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dft technique for avoiding contention/conflict in logic built-in se...
- Patent number 7,096,397
- Issue date Aug 22, 2006
- Intel Corporation
- Sandip Kundu
- G11 - INFORMATION STORAGE
Information Patent Grant
Generalized fault model for defects and circuit marginalities
- Patent number 7,036,063
- Issue date Apr 25, 2006
- Intel Corporation
- Sandip Kundu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for modeling and circuits with asynchronous be...
- Patent number 6,973,422
- Issue date Dec 6, 2005
- Intel Corporation
- Sitaram Yadavalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan design for double-edge-triggered flip-flops
- Patent number 6,938,225
- Issue date Aug 30, 2005
- Intel Corporation
- Sandip Kundu
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for power supply noise modeling and test patte...
- Patent number 6,912,701
- Issue date Jun 28, 2005
- Intel Corporation
- Sandip Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for rearranging plurality of memory storage elements in a co...
- Patent number 6,715,091
- Issue date Mar 30, 2004
- Intel Corporation
- Sandip Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constrained signature-based test
- Patent number 6,510,398
- Issue date Jan 21, 2003
- Intel Corporation
- Sandip Kundu
- G01 - MEASURING TESTING
Information Patent Grant
Technique for sorting high frequency integrated circuits
- Patent number 5,796,751
- Issue date Aug 18, 1998
- International Business Machines Corporation
- Sandip Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for testing internal nodes of an integrated circu...
- Patent number 5,793,777
- Issue date Aug 11, 1998
- International Business Machines Corporation
- Sandip Kundu
- G01 - MEASURING TESTING
Information Patent Grant
CMOS transistor network to gate level model extractor for simulatio...
- Patent number 5,629,858
- Issue date May 13, 1997
- International Business Machines Corporation
- Sandip Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjustable weighted random test pattern generator for logic circuits
- Patent number 5,297,151
- Issue date Mar 22, 1994
- International Business Machines Corporation
- Matthias Gruetzner
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD FOR DETECTING OR REPAIRING MINIMUM DELAY ERRORS
- Publication number 20160173090
- Publication date Jun 16, 2016
- Intel Corporation
- Pascal A. Meinerzhagen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Testing integrated circuits using high bandwidth wireless technology
- Publication number 20060052075
- Publication date Mar 9, 2006
- Rajeshwar Galivanche
- G01 - MEASURING TESTING
Information Patent Application
Generalized fault model for defects and circuit marginalities
- Publication number 20040205436
- Publication date Oct 14, 2004
- Sandip Kundu
- G01 - MEASURING TESTING
Information Patent Application
Weight compression/decompression system
- Publication number 20040117710
- Publication date Jun 17, 2004
- Srinivas Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for power supply noise modeling and test patte...
- Publication number 20040088615
- Publication date May 6, 2004
- Sandip Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generalized fault model for defects and circuit marginalities
- Publication number 20040064773
- Publication date Apr 1, 2004
- Sandip Kundu
- G01 - MEASURING TESTING
Information Patent Application
Scan design for double-edge-triggered flip-flops
- Publication number 20040041610
- Publication date Mar 4, 2004
- Sandip Kundu
- G01 - MEASURING TESTING
Information Patent Application
Simulation-based technique for contention avoidance in automatic te...
- Publication number 20030188273
- Publication date Oct 2, 2003
- Intel Corporation
- Sandip Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dft technique for avoiding contention/conflict in logic built-in se...
- Publication number 20030053358
- Publication date Mar 20, 2003
- Intel Corporation
- Sandip Kundu
- G11 - INFORMATION STORAGE

Sandip Kundu

Person

Patents Grantslast 30 patents

Apparatus and method for detecting or repairing minimum delay errors

Weight compression/decompression system

Dft technique for avoiding contention/conflict in logic built-in se...

Generalized fault model for defects and circuit marginalities

Method and apparatus for modeling and circuits with asynchronous be...

Scan design for double-edge-triggered flip-flops

Method and apparatus for power supply noise modeling and test patte...

System for rearranging plurality of memory storage elements in a co...

Constrained signature-based test

Technique for sorting high frequency integrated circuits

System and method for testing internal nodes of an integrated circu...

CMOS transistor network to gate level model extractor for simulatio...

Adjustable weighted random test pattern generator for logic circuits

Patents Applicationslast 30 patents

APPARATUS AND METHOD FOR DETECTING OR REPAIRING MINIMUM DELAY ERRORS

Testing integrated circuits using high bandwidth wireless technology

Generalized fault model for defects and circuit marginalities

Weight compression/decompression system

Method and apparatus for power supply noise modeling and test patte...

Generalized fault model for defects and circuit marginalities

Scan design for double-edge-triggered flip-flops

Simulation-based technique for contention avoidance in automatic te...

Dft technique for avoiding contention/conflict in logic built-in se...