Sanford CHU

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor structure including capacitors having different capac...
- Patent number 9,530,833
- Issue date Dec 27, 2016
- GLOBALFOUNDARIES INC.
- Dina H. Triyoso
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
P-channel flash with enhanced band-to-band tunneling hot electron i...
- Patent number 9,029,227
- Issue date May 12, 2015
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Eng Huat Toh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High voltage FINFET structure
- Patent number 9,006,055
- Issue date Apr 14, 2015
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Han Xiao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Channel surface technique for fabrication of FinFET devices
- Patent number 8,896,072
- Issue date Nov 25, 2014
- GLOBALFOUNDRIES Singapore Pte, Ltd.
- Chung Foong Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EEPROM cell
- Patent number 8,664,708
- Issue date Mar 4, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Sung Mun Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Dielectric stack
- Patent number 8,664,711
- Issue date Mar 4, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Sung Mun Jung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EEPROM cell
- Patent number 8,659,067
- Issue date Feb 25, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Sung Mun Jung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetrical transistor device and method of fabrication
- Patent number 8,629,503
- Issue date Jan 14, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Chung Foong Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric stack
- Patent number 8,541,273
- Issue date Sep 24, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Sung Mun Jung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure including high voltage device
- Patent number 8,410,553
- Issue date Apr 2, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Jeoung Mo Koo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EEPROM cell
- Patent number 8,383,475
- Issue date Feb 26, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Sung Mun Jung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EEPROM cell
- Patent number 8,383,476
- Issue date Feb 26, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Sung Mun Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Channel surface technique for fabrication of FinFET devices
- Patent number 8,349,692
- Issue date Jan 8, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Chung Foong Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LDMOS using a combination of enhanced dielectric stress layer and d...
- Patent number 8,334,567
- Issue date Dec 18, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Sanford Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Diffusion barrier and method of formation thereof
- Patent number 8,324,031
- Issue date Dec 4, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Shyue Seng Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance LDMOS device having enhanced dielectric strain layer
- Patent number 8,293,614
- Issue date Oct 23, 2012
- GlobalFoundries Singapore Pte. Ltd.
- Sanford Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance LDMOS device having enhanced dielectric strain layer
- Patent number 8,163,621
- Issue date Apr 24, 2012
- GlobalFoundries Singapore Pte. Ltd.
- Sanford Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetrical transistor device and method of fabrication
- Patent number 8,110,470
- Issue date Feb 7, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Chung Foong Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure including high voltage device
- Patent number 7,867,862
- Issue date Jan 11, 2011
- Chartered Semiconductor Manufacturing, Ltd.
- Jeoung Mo Koo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned vertical PNP transistor for high performance SiGe CBiC...
- Patent number 7,846,805
- Issue date Dec 7, 2010
- Chartered Semiconductor Manufacturing, Ltd.
- Shaoqiang Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LDMOS using a combination of enhanced dielectric stress layer and d...
- Patent number 7,824,968
- Issue date Nov 2, 2010
- Chartered Semiconductor Manufacturing Ltd.
- Sanford Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned vertical PNP transistor for high performance SiGe CBiC...
- Patent number 7,488,662
- Issue date Feb 10, 2009
- Chartered Semiconductor Manufacturing, Ltd.
- Shaoqiang Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of integrating triple gate oxide thickness
- Patent number 7,410,874
- Issue date Aug 12, 2008
- Chartered Semiconductor Manufacturing, Ltd.
- Purakh Raj Verma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOSFET device with low gate contact resistance
- Patent number 7,382,027
- Issue date Jun 3, 2008
- Chartered Semiconductor Manufacturing, Ltd.
- Purakh Raj Verma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form both high and low-k materials over the same dielectr...
- Patent number 7,323,736
- Issue date Jan 29, 2008
- Chartered Semiconductor Manufacturing Ltd.
- Pradeep Yelehanka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process to reduce substrate effects by forming channels under induc...
- Patent number 7,250,669
- Issue date Jul 31, 2007
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form both high and low-k materials over the same dielectr...
- Patent number 7,060,193
- Issue date Jun 13, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Pradeep Yelehanka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of a selective hard mask for the integration of double diffused...
- Patent number 6,933,188
- Issue date Aug 23, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Purakh Raj Verma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fill a trench and tunnel by using ALD seed layer and elec...
- Patent number 6,903,013
- Issue date Jun 7, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process to reduce substrate effects by forming channels under induc...
- Patent number 6,869,884
- Issue date Mar 22, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR STRUCTURE INCLUDING CAPACITORS HAVING DIFFERENT CAPAC...
- Publication number 20150364535
- Publication date Dec 17, 2015
- GLOBALFOUNDRIES INC.
- Dina H. Triyoso
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIFFUSION BARRIER AND METHOD OF FORMATION THEREOF
- Publication number 20150008528
- Publication date Jan 8, 2015
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Shyue Seng TAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH VOLTAGE FINFET STRUCTURE
- Publication number 20140210009
- Publication date Jul 31, 2014
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Han Xiao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC STACK
- Publication number 20140001538
- Publication date Jan 2, 2014
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Sung Mun JUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHANNEL SURFACE TECHNIQUE FOR FABRICATION OF FinFET DEVICES
- Publication number 20130187242
- Publication date Jul 25, 2013
- Globalfoundries Singapore PTE, LTD.
- Chung Foong Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EEPROM CELL
- Publication number 20130161720
- Publication date Jun 27, 2013
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Sung Mun JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
EEPROM CELL
- Publication number 20130161721
- Publication date Jun 27, 2013
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Sung Mun JUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIFFUSION BARRIER AND METHOD OF FORMATION THEREOF
- Publication number 20130087889
- Publication date Apr 11, 2013
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Shyue Seng TAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHANNEL SURFACE TECHNIQUE FOR FABRICATION OF FinFET DEVICES
- Publication number 20120228676
- Publication date Sep 13, 2012
- Globalfoundries Singapore PTE, LTD.
- Chung Foong Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
P-CHANNEL FLASH WITH ENHANCED BAND-TO-BAND TUNNELING HOT ELECTRON I...
- Publication number 20120223318
- Publication date Sep 6, 2012
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Eng Huat Toh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ASYMMETRICAL TRANSISTOR DEVICE AND METHOD OF FABRICATION
- Publication number 20120139046
- Publication date Jun 7, 2012
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Chung Foong TAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER
- Publication number 20120119293
- Publication date May 17, 2012
- Chartered Semiconductor Manufacturing Ltd.
- Sanford Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EEPROM CELL
- Publication number 20120074482
- Publication date Mar 29, 2012
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Sung Mun JUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC STACK
- Publication number 20120074537
- Publication date Mar 29, 2012
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Sung Mun JUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EEPROM CELL
- Publication number 20120074483
- Publication date Mar 29, 2012
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Sung Mun JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE
- Publication number 20110079850
- Publication date Apr 7, 2011
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Jeoung Mo KOO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ASYMMETRICAL TRANSISTOR DEVICE AND METHOD OF FABRICATION
- Publication number 20110049625
- Publication date Mar 3, 2011
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Chung Foong TAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LDMOS Using A Combination of Enhanced Dielectric Stress Layer and D...
- Publication number 20110042743
- Publication date Feb 24, 2011
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Sanford CHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MODULAR & SCALABLE INTRA-METAL CAPACITORS
- Publication number 20100038752
- Publication date Feb 18, 2010
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Chit Hwei NG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIFFUSION BARRIER AND METHOD OF FORMATION THEREOF
- Publication number 20090315152
- Publication date Dec 24, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Shyue Seng TAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER
- Publication number 20090302385
- Publication date Dec 10, 2009
- Sanford Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED VERTICAL PNP TRANSISTOR FOR HIGH PERFORMANCE SiGe CBiC...
- Publication number 20090146258
- Publication date Jun 11, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Shaoqiang ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE
- Publication number 20090072310
- Publication date Mar 19, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Jeoung Mo KOO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of integrating triple gate oxide thickness
- Publication number 20080124872
- Publication date May 29, 2008
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Purakh Raj Verma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LDMOS using a combination of enhanced dielectric stress layer and d...
- Publication number 20080014690
- Publication date Jan 17, 2008
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Sanford Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SHIELD STRUCTURE AND METHOD OF FABRICATION THEREOF
- Publication number 20070268093
- Publication date Nov 22, 2007
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Suh Fei LIM
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Self-aligned vertical PNP transistor for high performance SiGe CBiC...
- Publication number 20070134854
- Publication date Jun 14, 2007
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Shaoqiang Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to form both high and low-k materials over the same dielectr...
- Publication number 20060207965
- Publication date Sep 21, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Yelehanka Ramaghandramurthy Pradeep
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of making direct contact on gate by using dielectric stop layer
- Publication number 20050136573
- Publication date Jun 23, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Purakh Rajverma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming an inductor with continuous metal deposition
- Publication number 20050124131
- Publication date Jun 9, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Chit Hweing
- H01 - BASIC ELECTRIC ELEMENTS

Sanford CHU

Person

Patents Grantslast 30 patents

Semiconductor structure including capacitors having different capac...

P-channel flash with enhanced band-to-band tunneling hot electron i...

High voltage FINFET structure

Channel surface technique for fabrication of FinFET devices

EEPROM cell

Dielectric stack

EEPROM cell

Asymmetrical transistor device and method of fabrication

Dielectric stack

Semiconductor structure including high voltage device

EEPROM cell

EEPROM cell

Channel surface technique for fabrication of FinFET devices

LDMOS using a combination of enhanced dielectric stress layer and d...

Diffusion barrier and method of formation thereof

High performance LDMOS device having enhanced dielectric strain layer

High performance LDMOS device having enhanced dielectric strain layer

Asymmetrical transistor device and method of fabrication

Semiconductor structure including high voltage device

Self-aligned vertical PNP transistor for high performance SiGe CBiC...

LDMOS using a combination of enhanced dielectric stress layer and d...

Self-aligned vertical PNP transistor for high performance SiGe CBiC...

Method of integrating triple gate oxide thickness

MOSFET device with low gate contact resistance

Method to form both high and low-k materials over the same dielectr...

Process to reduce substrate effects by forming channels under induc...

Method to form both high and low-k materials over the same dielectr...

Use of a selective hard mask for the integration of double diffused...

Method to fill a trench and tunnel by using ALD seed layer and elec...

Process to reduce substrate effects by forming channels under induc...

Patents Applicationslast 30 patents

SEMICONDUCTOR STRUCTURE INCLUDING CAPACITORS HAVING DIFFERENT CAPAC...

DIFFUSION BARRIER AND METHOD OF FORMATION THEREOF

HIGH VOLTAGE FINFET STRUCTURE

DIELECTRIC STACK

CHANNEL SURFACE TECHNIQUE FOR FABRICATION OF FinFET DEVICES

EEPROM CELL

EEPROM CELL

DIFFUSION BARRIER AND METHOD OF FORMATION THEREOF

CHANNEL SURFACE TECHNIQUE FOR FABRICATION OF FinFET DEVICES

P-CHANNEL FLASH WITH ENHANCED BAND-TO-BAND TUNNELING HOT ELECTRON I...

ASYMMETRICAL TRANSISTOR DEVICE AND METHOD OF FABRICATION

HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER

EEPROM CELL

DIELECTRIC STACK

EEPROM CELL

SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE

ASYMMETRICAL TRANSISTOR DEVICE AND METHOD OF FABRICATION

LDMOS Using A Combination of Enhanced Dielectric Stress Layer and D...

MODULAR & SCALABLE INTRA-METAL CAPACITORS

DIFFUSION BARRIER AND METHOD OF FORMATION THEREOF

HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER

SELF-ALIGNED VERTICAL PNP TRANSISTOR FOR HIGH PERFORMANCE SiGe CBiC...

SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE

Method of integrating triple gate oxide thickness

LDMOS using a combination of enhanced dielectric stress layer and d...

INTEGRATED CIRCUIT SHIELD STRUCTURE AND METHOD OF FABRICATION THEREOF

Self-aligned vertical PNP transistor for high performance SiGe CBiC...

Method to form both high and low-k materials over the same dielectr...

Method of making direct contact on gate by using dielectric stop layer

Method of forming an inductor with continuous metal deposition