Sangki Hong

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Fiducial scheme adapted for stacked integrated circuits
- Patent number 8,222,121
- Issue date Jul 17, 2012
- Tezzaron Semiconductor, Inc.
- Robert Patti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for bonding wafers to produce stacked integrated circuits
- Patent number 8,183,127
- Issue date May 22, 2012
- Tezzaron Semiconductor, Inc.
- Robert Patti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fiducial scheme adapted for stacked integrated circuits
- Patent number 7,898,095
- Issue date Mar 1, 2011
- Tezzaron Semiconductor, Inc.
- Robert Patti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for bonding wafers to produce stacked integrated circuits
- Patent number 7,750,488
- Issue date Jul 6, 2010
- Tezzaron Semiconductor, Inc.
- Robert Patti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-metallic barrier formations for copper damascene type interconn...
- Patent number 6,566,260
- Issue date May 20, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-metallic barrier formations for copper damascene type interconn...
- Patent number 6,531,390
- Issue date Mar 11, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-metallic barrier formations for copper damascene type interconn...
- Patent number 6,489,233
- Issue date Dec 3, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non metallic barrier formations for copper damascene type interconn...
- Patent number 6,429,122
- Issue date Aug 6, 2002
- Chartered Semiconductor Manufacturing, Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Aluminum and copper bimetallic bond pad scheme for copper damascene...
- Patent number 6,376,353
- Issue date Apr 23, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Mei Sheng Zhou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite silicon-metal nitride barrier to prevent formation of met...
- Patent number 6,372,636
- Issue date Apr 16, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reversed damascene process for multiple level metal interconnects
- Patent number 6,352,917
- Issue date Mar 5, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Subhash Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-metallic barrier formation for copper damascene type interconnects
- Patent number 6,284,657
- Issue date Sep 4, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective etching of unreacted nickel after salicidation
- Patent number 6,225,202
- Issue date May 1, 2001
- Chartered Semiconductor Manufacturing, Ltd.
- Subhash Gupta
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Patents Applicationslast 30 patents

Information Patent Application
Fiducial Scheme Adapted for Stacked Integrated Circuits
- Publication number 20110117701
- Publication date May 19, 2011
- Robert Patti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Bonding Wafers to Produce Stacked Integrated Circuits
- Publication number 20100233850
- Publication date Sep 16, 2010
- Robert Patti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for bonding wafers to produce stacked integrated circuits
- Publication number 20080006938
- Publication date Jan 10, 2008
- Robert Patti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fiducial scheme adapted for stacked integrated circuits
- Publication number 20070216041
- Publication date Sep 20, 2007
- Robert Patti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for bonding wafers to produce stacked integrated circuits
- Publication number 20050224921
- Publication date Oct 13, 2005
- Subhash Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for bonding wafers to produce stacked integrated circuits
- Publication number 20020163072
- Publication date Nov 7, 2002
- Subhash Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to form self-aligned anti-via interconnects
- Publication number 20020155693
- Publication date Oct 24, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Sangki Hong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non metallic barrier formations for copper damascene type interconn...
- Publication number 20020001952
- Publication date Jan 3, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non metallic barrier formations for copper damascene type interconn...
- Publication number 20020001951
- Publication date Jan 3, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-conductive barrier formations for copper damascene type interco...
- Publication number 20010055878
- Publication date Dec 27, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-metallic barrier formations for copper damascene type interconn...
- Publication number 20010049195
- Publication date Dec 6, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS

Sangki Hong

Person

Patents Grantslast 30 patents

Fiducial scheme adapted for stacked integrated circuits

Method for bonding wafers to produce stacked integrated circuits

Fiducial scheme adapted for stacked integrated circuits

Method for bonding wafers to produce stacked integrated circuits

Non-metallic barrier formations for copper damascene type interconn...

Non-metallic barrier formations for copper damascene type interconn...

Non-metallic barrier formations for copper damascene type interconn...

Non metallic barrier formations for copper damascene type interconn...

Aluminum and copper bimetallic bond pad scheme for copper damascene...

Composite silicon-metal nitride barrier to prevent formation of met...

Reversed damascene process for multiple level metal interconnects

Non-metallic barrier formation for copper damascene type interconnects

Selective etching of unreacted nickel after salicidation

Patents Applicationslast 30 patents

Fiducial Scheme Adapted for Stacked Integrated Circuits

Method for Bonding Wafers to Produce Stacked Integrated Circuits

Method for bonding wafers to produce stacked integrated circuits

Fiducial scheme adapted for stacked integrated circuits

Method for bonding wafers to produce stacked integrated circuits

Method for bonding wafers to produce stacked integrated circuits

Method to form self-aligned anti-via interconnects

Non metallic barrier formations for copper damascene type interconn...

Non metallic barrier formations for copper damascene type interconn...

Non-conductive barrier formations for copper damascene type interco...

Non-metallic barrier formations for copper damascene type interconn...