Sanjay Gupta

Person

Noida, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Bandwidth test in networking System-on-Chip verification
- Patent number 10,664,566
- Issue date May 26, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency test in networking system-on-chip verification
- Patent number 10,657,217
- Issue date May 19, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flow control in networking system-on-chip verification
- Patent number 10,628,548
- Issue date Apr 21, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Traffic shaping in networking system-on-chip verification
- Patent number 10,521,544
- Issue date Dec 31, 2019
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Target capture and replay in emulation
- Patent number 10,503,848
- Issue date Dec 10, 2019
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Content addressable memory modeling in emulation and prototyping
- Patent number 10,410,713
- Issue date Sep 10, 2019
- Mentor Graphics Corporation
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power corruption of memory in emulation
- Patent number 9,990,452
- Issue date Jun 5, 2018
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid compilation for FPGA prototyping
- Patent number 9,959,379
- Issue date May 1, 2018
- Mentor Graphics Corporation
- Sanjay Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic control of design clock generation in emulation
- Patent number 9,946,823
- Issue date Apr 17, 2018
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modeling memory in emulation based on cache
- Patent number 9,898,563
- Issue date Feb 20, 2018
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Target capture and replay in emulation
- Patent number 9,767,237
- Issue date Sep 19, 2017
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Third party component debugging for integrated circuit design
- Patent number 9,619,600
- Issue date Apr 11, 2017
- Mentor Graphics Corporation
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Switching activity reduction through retiming
- Patent number 9,305,126
- Issue date Apr 5, 2016
- Mentor Graphics Corporation
- Charles W. Selvidge
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive clock management in emulation
- Patent number 9,165,099
- Issue date Oct 20, 2015
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for rule-based automatic layout parasitic extr...
- Patent number 8,650,518
- Issue date Feb 11, 2014
- Cadence Design Systems, Inc.
- Utpal Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register transfer level design compilation advisor
- Patent number 8,516,411
- Issue date Aug 20, 2013
- Mentor Graphics Corporation
- Sanjay Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compilation of remote procedure calls between a timed HDL model on...
- Patent number 7,260,798
- Issue date Aug 21, 2007
- Mentor Graphics Corporation
- Sanjay Gupta
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for hardware accelerated verification of digital...
- Patent number 7,257,802
- Issue date Aug 14, 2007
- Mentor Graphics Corporation
- Jyotirmoy Daw
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR MODELING MEMORY DEVICES WITH LATENCY
- Publication number 20220066801
- Publication date Mar 3, 2022
- Siemens Industry Software Inc.
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Traffic Shaping In Networking System-On-Chip Verification
- Publication number 20180113972
- Publication date Apr 26, 2018
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latency Test In Networking System-On-Chip Verification
- Publication number 20180113970
- Publication date Apr 26, 2018
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bandwidth Test In Networking System-On-Chip Verification
- Publication number 20180113961
- Publication date Apr 26, 2018
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flow Control In Networking System-On-Chip Verification
- Publication number 20180113976
- Publication date Apr 26, 2018
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUG ENVIRONMENT FOR A MULTI USER HARDWARE ASSISTED VERIFICATION S...
- Publication number 20180032357
- Publication date Feb 1, 2018
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Target Capture And Replay In Emulation
- Publication number 20170337309
- Publication date Nov 23, 2017
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modeling Memory In Emulation Based On Cache
- Publication number 20170140083
- Publication date May 18, 2017
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low Power Corruption Of Memory In Emulation
- Publication number 20170140084
- Publication date May 18, 2017
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Target Capture And Replay In Emulation
- Publication number 20170140082
- Publication date May 18, 2017
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hybrid Compilation For FPGA Prototyping
- Publication number 20170103156
- Publication date Apr 13, 2017
- Mentor Graphics Corporation
- Sanjay Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Switching Activity Reduction Through Retiming
- Publication number 20150269295
- Publication date Sep 24, 2015
- Mentor Graphics Corporation
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THIRD PARTY COMPONENT DEBUGGING FOR INTEGRATED CIRCUIT DESIGN
- Publication number 20150149973
- Publication date May 28, 2015
- Mentor Graphics Corporation
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptive Clock Management In Emulation
- Publication number 20150100931
- Publication date Apr 9, 2015
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Control Of Design Clock Generation In Emulation
- Publication number 20150046144
- Publication date Feb 12, 2015
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Register Transfer Level Design Compilation Advisor
- Publication number 20120180011
- Publication date Jul 12, 2012
- Sanjay Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR RULE-BASED AUTOMATIC LAYOUT PARASITIC EXTR...
- Publication number 20110173582
- Publication date Jul 14, 2011
- Cadence Design Systems, Inc.
- Utpal Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compilation of remote procedure calls between a timed HDL model on...
- Publication number 20050198606
- Publication date Sep 8, 2005
- Sanjay Gupta
- G01 - MEASURING TESTING
Information Patent Application
Method and system for hardware accelerated verification of digital...
- Publication number 20050144585
- Publication date Jun 30, 2005
- Jyotirmoy Daw
- G06 - COMPUTING CALCULATING COUNTING

Sanjay Gupta

Person

Patents Grantslast 30 patents

Bandwidth test in networking System-on-Chip verification

Latency test in networking system-on-chip verification

Flow control in networking system-on-chip verification

Traffic shaping in networking system-on-chip verification

Target capture and replay in emulation

Content addressable memory modeling in emulation and prototyping

Low power corruption of memory in emulation

Hybrid compilation for FPGA prototyping

Dynamic control of design clock generation in emulation

Modeling memory in emulation based on cache

Target capture and replay in emulation

Third party component debugging for integrated circuit design

Switching activity reduction through retiming

Adaptive clock management in emulation

Method and apparatus for rule-based automatic layout parasitic extr...

Register transfer level design compilation advisor

Compilation of remote procedure calls between a timed HDL model on...

Method and system for hardware accelerated verification of digital...

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR MODELING MEMORY DEVICES WITH LATENCY

Traffic Shaping In Networking System-On-Chip Verification

Latency Test In Networking System-On-Chip Verification

Bandwidth Test In Networking System-On-Chip Verification

Flow Control In Networking System-On-Chip Verification

DEBUG ENVIRONMENT FOR A MULTI USER HARDWARE ASSISTED VERIFICATION S...

Target Capture And Replay In Emulation

Modeling Memory In Emulation Based On Cache

Low Power Corruption Of Memory In Emulation

Target Capture And Replay In Emulation

Hybrid Compilation For FPGA Prototyping

Switching Activity Reduction Through Retiming

THIRD PARTY COMPONENT DEBUGGING FOR INTEGRATED CIRCUIT DESIGN

Adaptive Clock Management In Emulation

Dynamic Control Of Design Clock Generation In Emulation

Register Transfer Level Design Compilation Advisor

METHOD AND APPARATUS FOR RULE-BASED AUTOMATIC LAYOUT PARASITIC EXTR...

Compilation of remote procedure calls between a timed HDL model on...

Method and system for hardware accelerated verification of digital...