Sanjay Kumar Murugan

Person

Malacca, MY

People

Patents Grantslast 30 patents

Information Patent Grant
Chip package and semiconductor arrangement having thermally conduct...
- Patent number 12,068,213
- Issue date Aug 20, 2024
- Infineon Technologies AG
- Thai Kee Gan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power semiconductor device with dual heat dissipation structures
- Patent number 11,908,771
- Issue date Feb 20, 2024
- Infineon Technologies AG
- Jayaganasan Narayanasamy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Molded semiconductor module having a mold step for increasing creep...
- Patent number 11,621,204
- Issue date Apr 4, 2023
- Infineon Technologies AG
- Oliver Markus Kreiter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package lead design with grooves for improved dambar separation
- Patent number 11,362,023
- Issue date Jun 14, 2022
- Infineon Technologies AG
- Jayaganasan Narayanasamy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power semiconductor package and method for fabricating a power semi...
- Patent number 11,211,356
- Issue date Dec 28, 2021
- Infineon Technologies AG
- Wee Aun Jason Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a matrix composite layer and workpiece with a ma...
- Patent number 10,457,001
- Issue date Oct 29, 2019
- Infineon Technologies AG
- Jayaganasan Narayanasamy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Rivetless lead fastening for a semiconductor package
- Patent number 10,431,526
- Issue date Oct 1, 2019
- Cree, Inc.
- Kar Meng Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Spatially selective roughening of encapsulant to promote adhesion w...
- Patent number 10,347,554
- Issue date Jul 9, 2019
- Infineon Technologies AG
- Norbert Joson Santos
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip package having contact pins at short side edges
- Patent number 10,037,934
- Issue date Jul 31, 2018
- Infineon Technologies Austria AG
- Ralf Otremba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Functionalized interface structure
- Patent number 9,922,910
- Issue date Mar 20, 2018
- Infineon Technologies Austria AG
- Ralf Otremba
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR PACKAGE AND RELATED METHODS OF MANUFACTURING
- Publication number 20240145340
- Publication date May 2, 2024
- INFINEON TECHNOLOGIES AG
- Jayaganasan Narayanasamy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL FUNCTIONAL THERMAL PERFORMANCE SEMICONDUCTOR PACKAGE AND RELAT...
- Publication number 20230154827
- Publication date May 18, 2023
- INFINEON TECHNOLOGIES AG
- Jayaganasan Narayanasamy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOLDED SEMICONDUCTOR MODULE HAVING A MOLD STEP FOR INCREASING CREEP...
- Publication number 20220262693
- Publication date Aug 18, 2022
- Oliver Markus Kreiter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE, SEMICONDUCTOR ARRANGEMENT, METHOD OF FORMING A CHIP P...
- Publication number 20220173006
- Publication date Jun 2, 2022
- Thai Kee Gan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING A POWER SEMI...
- Publication number 20220115245
- Publication date Apr 14, 2022
- Jayaganasan Narayanasamy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Power Semiconductor Package and Method for Fabricating a Power Semi...
- Publication number 20210057375
- Publication date Feb 25, 2021
- Wee Aun Jason Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Package Lead Design with Grooves for Improved Dambar Separation
- Publication number 20210013135
- Publication date Jan 14, 2021
- Jayaganasan Narayanasamy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Rivetless Lead Fastening for a Semiconductor Package
- Publication number 20190109070
- Publication date Apr 11, 2019
- INFINEON TECHNOLOGIES AG
- Kar Meng Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Matrix Composite Layer and Workpiece With a Ma...
- Publication number 20180297301
- Publication date Oct 18, 2018
- INFINEON TECHNOLOGIES AG
- Jayaganasan Narayanasamy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Spatially selective roughening of encapsulant to promote adhesion w...
- Publication number 20170271229
- Publication date Sep 21, 2017
- INFINEON TECHNOLOGIES AG
- Norbert Joson SANTOS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electronic Devices with Increased Creepage Distances
- Publication number 20160365296
- Publication date Dec 15, 2016
- INFINEON TECHNOLOGIES AG
- Ralf Otremba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Chip Package Having Contact Pins at Short Side Edges
- Publication number 20160233149
- Publication date Aug 11, 2016
- Infineon Technologies Austria AG
- Ralf Otremba
- H01 - BASIC ELECTRIC ELEMENTS

Sanjay Kumar Murugan

Person

Patents Grantslast 30 patents

Chip package and semiconductor arrangement having thermally conduct...

Power semiconductor device with dual heat dissipation structures

Molded semiconductor module having a mold step for increasing creep...

Package lead design with grooves for improved dambar separation

Power semiconductor package and method for fabricating a power semi...

Method for forming a matrix composite layer and workpiece with a ma...

Rivetless lead fastening for a semiconductor package

Spatially selective roughening of encapsulant to promote adhesion w...

Semiconductor chip package having contact pins at short side edges

Functionalized interface structure

Patents Applicationslast 30 patents

SEMICONDUCTOR PACKAGE AND RELATED METHODS OF MANUFACTURING

DUAL FUNCTIONAL THERMAL PERFORMANCE SEMICONDUCTOR PACKAGE AND RELAT...

MOLDED SEMICONDUCTOR MODULE HAVING A MOLD STEP FOR INCREASING CREEP...

CHIP PACKAGE, SEMICONDUCTOR ARRANGEMENT, METHOD OF FORMING A CHIP P...

POWER SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING A POWER SEMI...

Power Semiconductor Package and Method for Fabricating a Power Semi...

Package Lead Design with Grooves for Improved Dambar Separation

Rivetless Lead Fastening for a Semiconductor Package

Method for Forming a Matrix Composite Layer and Workpiece With a Ma...

Spatially selective roughening of encapsulant to promote adhesion w...

Electronic Devices with Increased Creepage Distances

Semiconductor Chip Package Having Contact Pins at Short Side Edges