Sanjay Ramakrishna Pillay

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Parallel fault simulator with back propagation enhancement
- Patent number 11,036,604
- Issue date Jun 15, 2021
- SIEMENS INDUSTRY SOFTWARE INC.
- Sanjay Pillay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional safety synthesis
- Patent number 10,796,047
- Issue date Oct 6, 2020
- Mentor Graphics Corporation
- Sanjay Pillay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault campaign in mixed signal environment
- Patent number 10,775,430
- Issue date Sep 15, 2020
- Mentor Graphics Corporation
- Sanjay Pillay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for analyzing failure rates due to soft/hard er...
- Patent number 10,768,227
- Issue date Sep 8, 2020
- Mentor Graphics Corporation
- Sanjay Pillay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power VLSI designs using circuit failure in sequential cells as...
- Patent number 10,522,237
- Issue date Dec 31, 2019
- Mentor Graphics Corporation
- Sanjay Pillay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for analyzing soft errors in a design and reduc...
- Patent number 9,991,008
- Issue date Jun 5, 2018
- Austemper Design Systems Inc.
- Sanjay Pillay
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for predicting compressibility of data
- Patent number 9,710,166
- Issue date Jul 18, 2017
- Western Digital Technologies, Inc.
- Wei Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan cells with minimized shoot-through and scan chains and integra...
- Patent number 7,747,917
- Issue date Jun 29, 2010
- Cirrus Logic, Inc.
- Richard Putman
- G01 - MEASURING TESTING
Information Patent Grant
Processor and processing method for reusing arbitrary sections of p...
- Patent number 7,596,681
- Issue date Sep 29, 2009
- Cirrus Logic, Inc.
- Ronald D. Wiese
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for reducing noise during video deinterlacing
- Patent number 7,538,824
- Issue date May 26, 2009
- Magnum Semiconductor, Inc.
- Sanjay R. Pillay
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuits and methods for deinterlacing video display data and syste...
- Patent number 7,522,214
- Issue date Apr 21, 2009
- Magnum Semiconductor, Inc.
- Sanjay R. Pillay
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Circuits and methods for detecting 2:2 encoded video and systems ut...
- Patent number 7,450,184
- Issue date Nov 11, 2008
- Magnum Semiconductor, Inc.
- Sanjay R. Pillay
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for detecting a change in a sequence of interla...
- Patent number 7,420,626
- Issue date Sep 2, 2008
- Magnum Semiconductor, Inc.
- Sanjay R. Pillay
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for display object edge detection and pixel dat...
- Patent number 7,414,671
- Issue date Aug 19, 2008
- Magnum Semiconductor, Inc.
- William Lynn Gallagher
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuits and methods for power management in a processor-based syst...
- Patent number 7,000,138
- Issue date Feb 14, 2006
- Cirrus Logic, Inc.
- Sanjay Ramakrishna Pillay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits and methods for debugging an embedded processor and system...
- Patent number 6,948,098
- Issue date Sep 20, 2005
- Cirrus Logic, Inc.
- Sanjay Ramakrishna Pillay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variable duty cycle clock generation circuits and methods and syste...
- Patent number 6,847,244
- Issue date Jan 25, 2005
- Cirrus Logic, Inc.
- Sanjay Pillay
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuits and methods for extracting a clock from a biphase encoded...
- Patent number 6,782,300
- Issue date Aug 24, 2004
- Cirrus Logic, Inc.
- Sanjay Ramakrishna Pillay
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuits for controlling a bidirectional terminal and systems using...
- Patent number 6,359,315
- Issue date Mar 19, 2002
- Cirrus Logic, Inc.
- Sanjay Pillay
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
FUNCTIONAL SAFETY SYNTHESIS
- Publication number 20190228125
- Publication date Jul 25, 2019
- Mentor Graphics Corporation
- Sanjay Pillay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULT CAMPAIGN IN MIXED SIGNAL ENVIRONMENT
- Publication number 20190187207
- Publication date Jun 20, 2019
- Mentor Graphics Corporation
- Sanjay Pillay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL FAULT SIMULATOR WITH BACK PROPAGATION ENHANCEMENT
- Publication number 20190171539
- Publication date Jun 6, 2019
- Mentor Graphics Corporation
- Sanjay Pillay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR ANALYZING FAILURE RATES DUE TO SOFT/HARD ER...
- Publication number 20180364306
- Publication date Dec 20, 2018
- Austemper Design Systems Inc.
- Sanjay Pillay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER VLSI DESIGNS USING CIRCUIT FAILURE IN SEQUENTIAL CELLS AS...
- Publication number 20170212972
- Publication date Jul 27, 2017
- Austemper Design Systems Inc.
- Sanjay Pillay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR ANALYZING SOFT ERRORS IN A DESIGN AND REDUC...
- Publication number 20170213602
- Publication date Jul 27, 2017
- Austemper Design Systems Inc.
- Sanjay Pillay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR PREDICTING COMPRESSIBILITY OF DATA
- Publication number 20160306561
- Publication date Oct 20, 2016
- HGST NETHERLANDS B.V.
- Wei Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scan cells with minimized shoot-through and scan chains and integra...
- Publication number 20080307280
- Publication date Dec 11, 2008
- Richard Putman
- G01 - MEASURING TESTING
Information Patent Application
Processor and processing method for reusing arbitrary sections of p...
- Publication number 20070239973
- Publication date Oct 11, 2007
- Ronald D. Wiese
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Variable duty cycle clock generation circuits and methods and syste...
- Publication number 20040135608
- Publication date Jul 15, 2004
- Cirrus Logic, Inc.
- Sanjay Pillay
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuits and methods for extracting a clock from a biphase encoded...
- Publication number 20030195645
- Publication date Oct 16, 2003
- Cirrus Logic, Inc.
- Sanjay Ramakrishna Pillay
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Circuits and methods for debugging an embedded processor and system...
- Publication number 20030051192
- Publication date Mar 13, 2003
- Sanjay Ramakrishna Pillay
- G01 - MEASURING TESTING

Sanjay Ramakrishna Pillay

Person

Patents Grantslast 30 patents

Parallel fault simulator with back propagation enhancement

Functional safety synthesis

Fault campaign in mixed signal environment

Systems and methods for analyzing failure rates due to soft/hard er...

Low power VLSI designs using circuit failure in sequential cells as...

Systems and methods for analyzing soft errors in a design and reduc...

Systems and methods for predicting compressibility of data

Scan cells with minimized shoot-through and scan chains and integra...

Processor and processing method for reusing arbitrary sections of p...

Systems and methods for reducing noise during video deinterlacing

Circuits and methods for deinterlacing video display data and syste...

Circuits and methods for detecting 2:2 encoded video and systems ut...

Systems and methods for detecting a change in a sequence of interla...

Systems and methods for display object edge detection and pixel dat...

Circuits and methods for power management in a processor-based syst...

Circuits and methods for debugging an embedded processor and system...

Variable duty cycle clock generation circuits and methods and syste...

Circuits and methods for extracting a clock from a biphase encoded...

Circuits for controlling a bidirectional terminal and systems using...

Patents Applicationslast 30 patents

FUNCTIONAL SAFETY SYNTHESIS

FAULT CAMPAIGN IN MIXED SIGNAL ENVIRONMENT

PARALLEL FAULT SIMULATOR WITH BACK PROPAGATION ENHANCEMENT

SYSTEMS AND METHODS FOR ANALYZING FAILURE RATES DUE TO SOFT/HARD ER...

LOW POWER VLSI DESIGNS USING CIRCUIT FAILURE IN SEQUENTIAL CELLS AS...

SYSTEMS AND METHODS FOR ANALYZING SOFT ERRORS IN A DESIGN AND REDUC...

SYSTEMS AND METHODS FOR PREDICTING COMPRESSIBILITY OF DATA

Scan cells with minimized shoot-through and scan chains and integra...

Processor and processing method for reusing arbitrary sections of p...

Variable duty cycle clock generation circuits and methods and syste...

Circuits and methods for extracting a clock from a biphase encoded...

Circuits and methods for debugging an embedded processor and system...