Sanjeev Jain

Person

Schewsbury, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Technologies for adaptive network packet egress scheduling
- Patent number 11,489,789
- Issue date Nov 1, 2022
- Intel Corporation
- Carl Geoffrion
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Securing memory accesses in a virtualized environment
- Patent number 11,327,900
- Issue date May 10, 2022
- NVIDIA Corporation
- Samuel Hammond Duncan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for offloading data object replication and service fun...
- Patent number 11,082,515
- Issue date Aug 3, 2021
- Intel Corporation
- Dinesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Distributed address translation in a multi-node interconnect fabric
- Patent number 10,769,076
- Issue date Sep 8, 2020
- NVIDIA Corporation
- Samuel Hammond Duncan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined hash table with reduced collisions
- Patent number 10,621,080
- Issue date Apr 14, 2020
- Intel Corporation
- Sanjeev Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for network packet cache management
- Patent number 9,992,299
- Issue date Jun 5, 2018
- Intel Corporation
- Ren Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for network packet cache management
- Patent number 9,866,498
- Issue date Jan 9, 2018
- Intel Corporation
- Ren Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and method for hardware-accelerated packet processing
- Patent number 9,847,936
- Issue date Dec 19, 2017
- Intel Corporation
- Nrupal Jani
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for access control
- Patent number 9,794,263
- Issue date Oct 17, 2017
- Intel Corporation
- Sanjeev Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Device for indicating packet processing hints
- Patent number 9,742,616
- Issue date Aug 22, 2017
- Intel Corporation
- Nrupal Jani
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for network packet cache management
- Patent number 9,565,131
- Issue date Feb 7, 2017
- Intel Corporation
- Ren Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatuses and methods for deterministic pattern matching
- Patent number 8,370,274
- Issue date Feb 5, 2013
- Intel Corporation
- David K. Cassetti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lock sequencing to reorder and grant lock requests from multiple pr...
- Patent number 7,853,951
- Issue date Dec 14, 2010
- Intel Corporation
- Mark Rosenbluth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient sort scheme for a hierarchical scheduler
- Patent number 7,769,026
- Issue date Aug 3, 2010
- Intel Corporation
- Sanjeev Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques to manage flow control
- Patent number 7,554,908
- Issue date Jun 30, 2009
- Intel Corporation
- Sanjeev Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus to provide efficient communication between mul...
- Patent number 7,555,630
- Issue date Jun 30, 2009
- Intel Corporation
- Sanjeev Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for scheduling packets
- Patent number 7,522,620
- Issue date Apr 21, 2009
- Intel Corporation
- John Wishneusky
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus to support efficient check-point and role-back...
- Patent number 7,505,410
- Issue date Mar 17, 2009
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Providing access to data shared by packet processing threads
- Patent number 7,477,641
- Issue date Jan 13, 2009
- Intel Corporation
- Sanjeev Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having content addressable memory for block-based queue s...
- Patent number 7,467,256
- Issue date Dec 16, 2008
- Intel Corporation
- Sanjeev Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flexible mesh structure for hierarchical scheduling
- Patent number 7,460,544
- Issue date Dec 2, 2008
- Intel Corporation
- Sanjeev Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phasing for a multi-threaded network processor
- Patent number 7,441,245
- Issue date Oct 21, 2008
- Intel Corporation
- Donald F. Hooper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for scheduling packets
- Patent number 7,426,215
- Issue date Sep 16, 2008
- Intel Corporation
- David Romano
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Processor having content addressable memory with command ordering
- Patent number 7,418,543
- Issue date Aug 26, 2008
- Intel Corporation
- Sanjeev Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
Enqueueing entries in a packet queue referencing packets
- Patent number 7,366,865
- Issue date Apr 29, 2008
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to enable DRAM to support low-latency access v...
- Patent number 7,325,099
- Issue date Jan 29, 2008
- Intel Corporation
- Sanjeev Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network statistics
- Patent number 7,289,455
- Issue date Oct 30, 2007
- Intel Corporation
- Sanjeev Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus providing efficient queue descriptor memory ac...
- Patent number 7,277,990
- Issue date Oct 2, 2007
- Sanjeev Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Folding for a multi-threaded network processor
- Patent number 7,240,164
- Issue date Jul 3, 2007
- Intel Corporation
- Donald F. Hooper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Request queuing system for a PCI bridge
- Patent number 6,694,397
- Issue date Feb 17, 2004
- Intel Corporation
- Stanley A. Lackey
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SECURING MEMORY ACCESSES IN A VIRTUALIZED ENVIRONMENT
- Publication number 20200356492
- Publication date Nov 12, 2020
- NVIDIA Corporation
- Samuel Hammond Duncan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINED HASH TABLE WITH REDUCED COLLISIONS
- Publication number 20200159654
- Publication date May 21, 2020
- Intel Corporation
- Sanjeev Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED ADDRESS TRANSLATION IN A MULTI-NODE INTERCONNECT FABRIC
- Publication number 20200159669
- Publication date May 21, 2020
- NVIDIA Corporation
- Samuel Hammond Duncan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR ADAPTIVE NETWORK PACKET EGRESS SCHEDULING
- Publication number 20200007470
- Publication date Jan 2, 2020
- Intel Corporation
- Carl Geoffrion
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
APPARATUS AND METHOD FOR HARDWARE-ACCELERATED PACKET PROCESSING
- Publication number 20180337850
- Publication date Nov 22, 2018
- Intel Corporation
- Nrupal Jani
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PIPELINED HASH TABLE WITH REDUCED COLLISIONS
- Publication number 20170286006
- Publication date Oct 5, 2017
- Sanjeev Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR NETWORK PACKET CACHE MANAGEMENT
- Publication number 20170149926
- Publication date May 25, 2017
- Intel Corporation
- Ren Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR OFFLOADING DATA OBJECT REPLICATION AND SERVICE FUN...
- Publication number 20170094002
- Publication date Mar 30, 2017
- Dinesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNIQUES FOR SELECTIVELY REDUCING POWER LEVELS OF PORTS AND CORE...
- Publication number 20170075409
- Publication date Mar 16, 2017
- lntel Corporation
- Robert J. Woodruff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR HARDWARE-ACCELERATED PACKET PROCESSING
- Publication number 20160380885
- Publication date Dec 29, 2016
- Nrupal Jani
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR ACCESS CONTROL
- Publication number 20160191530
- Publication date Jun 30, 2016
- Sanjeev Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DEVICE FOR INDICATING PACKET PROCESSING HINTS
- Publication number 20160182408
- Publication date Jun 23, 2016
- Nrupal Jani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR NETWORK PACKET CACHE MANAGEMENT
- Publication number 20160182351
- Publication date Jun 23, 2016
- Ren Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Packet Boundary Spanning Pattern Matching Based At Least In Part Up...
- Publication number 20110145205
- Publication date Jun 16, 2011
- Sanjeev Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION
- Publication number 20100332877
- Publication date Dec 30, 2010
- Mark A. Yarch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR DETERMINISTIC PATTERN MATCHING
- Publication number 20100306263
- Publication date Dec 2, 2010
- David K. Cassetti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Program memory having flexible data storage capabilities
- Publication number 20080022175
- Publication date Jan 24, 2008
- Sanjeev Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient sort scheme for a hierarchical scheduler
- Publication number 20070223504
- Publication date Sep 27, 2007
- Sanjeev Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Inter-thread communication of lock protected data
- Publication number 20070044103
- Publication date Feb 22, 2007
- Mark Rosenbluth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Lock sequencing
- Publication number 20070022429
- Publication date Jan 25, 2007
- Mark Rosenbluth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to support efficient check-point and role-back...
- Publication number 20070008985
- Publication date Jan 11, 2007
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Providing access to data shared by packet processing threads
- Publication number 20060159103
- Publication date Jul 20, 2006
- Sanjeev Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for dynamically changing ring size in network...
- Publication number 20060153185
- Publication date Jul 13, 2006
- Intel Corporation
- Sanjeev Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus to provide efficient communication between pro...
- Publication number 20060155959
- Publication date Jul 13, 2006
- Sanjeev Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flexible mesh structure for hierarchical scheduling
- Publication number 20060140192
- Publication date Jun 29, 2006
- Intel Corporation, A DELAWARE CORPORATION
- Sanjeev Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method for packet queuing
- Publication number 20060140203
- Publication date Jun 29, 2006
- Sanjeev Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Processor having content addressable memory for block-based queue s...
- Publication number 20060143373
- Publication date Jun 29, 2006
- Sanjeev Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus to support multiple memory banks with a memory...
- Publication number 20060136681
- Publication date Jun 22, 2006
- Sanjeev Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor having content addressable memory with command ordering
- Publication number 20060136659
- Publication date Jun 22, 2006
- Sanjeev Jain
- G11 - INFORMATION STORAGE
Information Patent Application
Techniques to manage flow control
- Publication number 20060126512
- Publication date Jun 15, 2006
- Sanjeev Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Sanjeev Jain

Person

Patents Grantslast 30 patents

Technologies for adaptive network packet egress scheduling

Securing memory accesses in a virtualized environment

Technologies for offloading data object replication and service fun...

Distributed address translation in a multi-node interconnect fabric

Pipelined hash table with reduced collisions

Technologies for network packet cache management

Technologies for network packet cache management

Apparatus and method for hardware-accelerated packet processing

Technologies for access control

Device for indicating packet processing hints

Technologies for network packet cache management

Apparatuses and methods for deterministic pattern matching

Lock sequencing to reorder and grant lock requests from multiple pr...

Efficient sort scheme for a hierarchical scheduler

Techniques to manage flow control

Method and apparatus to provide efficient communication between mul...

Method and apparatus for scheduling packets

Method and apparatus to support efficient check-point and role-back...

Providing access to data shared by packet processing threads

Processor having content addressable memory for block-based queue s...

Flexible mesh structure for hierarchical scheduling

Phasing for a multi-threaded network processor

Method and apparatus for scheduling packets

Processor having content addressable memory with command ordering

Enqueueing entries in a packet queue referencing packets

Method and apparatus to enable DRAM to support low-latency access v...

Network statistics

Method and apparatus providing efficient queue descriptor memory ac...

Folding for a multi-threaded network processor

Request queuing system for a PCI bridge

Patents Applicationslast 30 patents

SECURING MEMORY ACCESSES IN A VIRTUALIZED ENVIRONMENT

PIPELINED HASH TABLE WITH REDUCED COLLISIONS

DISTRIBUTED ADDRESS TRANSLATION IN A MULTI-NODE INTERCONNECT FABRIC

TECHNOLOGIES FOR ADAPTIVE NETWORK PACKET EGRESS SCHEDULING

APPARATUS AND METHOD FOR HARDWARE-ACCELERATED PACKET PROCESSING

PIPELINED HASH TABLE WITH REDUCED COLLISIONS

TECHNOLOGIES FOR NETWORK PACKET CACHE MANAGEMENT

TECHNOLOGIES FOR OFFLOADING DATA OBJECT REPLICATION AND SERVICE FUN...

TECHNIQUES FOR SELECTIVELY REDUCING POWER LEVELS OF PORTS AND CORE...

APPARATUS AND METHOD FOR HARDWARE-ACCELERATED PACKET PROCESSING

TECHNOLOGIES FOR ACCESS CONTROL

DEVICE FOR INDICATING PACKET PROCESSING HINTS

TECHNOLOGIES FOR NETWORK PACKET CACHE MANAGEMENT

Packet Boundary Spanning Pattern Matching Based At Least In Part Up...

METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION

APPARATUSES AND METHODS FOR DETERMINISTIC PATTERN MATCHING

Program memory having flexible data storage capabilities

Efficient sort scheme for a hierarchical scheduler

Inter-thread communication of lock protected data

Lock sequencing

Method and apparatus to support efficient check-point and role-back...

Providing access to data shared by packet processing threads

Method and apparatus for dynamically changing ring size in network...

Method and apparatus to provide efficient communication between pro...

Flexible mesh structure for hierarchical scheduling

System and method for packet queuing

Processor having content addressable memory for block-based queue s...

Method and apparatus to support multiple memory banks with a memory...

Processor having content addressable memory with command ordering

Techniques to manage flow control