Sankaranarayanan Srinivasan

Person

Longmont, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Machine-learning enhanced compiler
- Patent number 11,853,662
- Issue date Dec 26, 2023
- Synopsys, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine-learning enhanced compiler
- Patent number 11,366,948
- Issue date Jun 21, 2022
- Synopsys, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch based optimization during implementation of circuit designs f...
- Patent number 8,146,041
- Issue date Mar 27, 2012
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and arrangement providing for implementation granularity usi...
- Patent number 8,141,010
- Issue date Mar 20, 2012
- Xilinx, Inc.
- Raymond Kong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design fitting
- Patent number 8,136,073
- Issue date Mar 13, 2012
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock speed for a digital circuit
- Patent number 8,024,696
- Issue date Sep 20, 2011
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch based optimization during implementation of circuit designs f...
- Patent number 8,010,923
- Issue date Aug 30, 2011
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Merging of equivalent logic blocks in a circuit design
- Patent number 7,984,415
- Issue date Jul 19, 2011
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement driven control set resynthesis
- Patent number 7,979,831
- Issue date Jul 12, 2011
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fanout-optimization during physical synthesis for placed circuit de...
- Patent number 7,853,914
- Issue date Dec 14, 2010
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient timing graph update for dynamic netlist changes
- Patent number 7,657,855
- Issue date Feb 2, 2010
- Xilinx, Inc.
- Walter A. Manaker, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cost-based performance driven legalization technique for placement...
- Patent number 7,636,876
- Issue date Dec 22, 2009
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a pre-implemented circuit des...
- Patent number 7,392,498
- Issue date Jun 24, 2008
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and arrangement providing for implementation granularity usi...
- Patent number 7,360,177
- Issue date Apr 15, 2008
- Xilinx, Inc.
- Raymond Kong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for designing integrated circuits using implement...
- Patent number 7,181,704
- Issue date Feb 20, 2007
- Xilinx, Inc.
- Daniel J. Downs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Alleviating timing based congestion within circuit designs
- Patent number 7,152,217
- Issue date Dec 19, 2006
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using router feedback for placement improvements for logic design
- Patent number 7,076,758
- Issue date Jul 11, 2006
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MACHINE-LEARNING ENHANCED COMPILER
- Publication number 20220318468
- Publication date Oct 6, 2022
- Synopsys, Inc.
- Sankaranarayanan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE-LEARNING ENHANCED COMPILER
- Publication number 20210117601
- Publication date Apr 22, 2021
- Synopsys, Inc.
- Sankaranarayanan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING

Sankaranarayanan Srinivasan

Person

Patents Grantslast 30 patents

Machine-learning enhanced compiler

Machine-learning enhanced compiler

Latch based optimization during implementation of circuit designs f...

Method and arrangement providing for implementation granularity usi...

Circuit design fitting

Clock speed for a digital circuit

Latch based optimization during implementation of circuit designs f...

Merging of equivalent logic blocks in a circuit design

Placement driven control set resynthesis

Fanout-optimization during physical synthesis for placed circuit de...

Efficient timing graph update for dynamic netlist changes

Cost-based performance driven legalization technique for placement...

Method and apparatus for implementing a pre-implemented circuit des...

Method and arrangement providing for implementation granularity usi...

Method and system for designing integrated circuits using implement...

Alleviating timing based congestion within circuit designs

Using router feedback for placement improvements for logic design

Patents Applicationslast 30 patents

MACHINE-LEARNING ENHANCED COMPILER

MACHINE-LEARNING ENHANCED COMPILER