Sasikanth Avancha

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Matrix operation optimization mechanism
- Patent number 12,039,000
- Issue date Jul 16, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Utilizing structured sparsity in systolic arrays
- Patent number 11,977,885
- Issue date May 7, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses, methods, and systems for access synchronization in a s...
- Patent number 11,681,529
- Issue date Jun 20, 2023
- Intel Corporation
- Swagath Venkataramani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instructions and logic for vector multiply add with zero skipping
- Patent number 11,669,329
- Issue date Jun 6, 2023
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Matrix operation optimization mechanism
- Patent number 11,593,454
- Issue date Feb 28, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instructions and logic for vector multiply add with zero skipping
- Patent number 11,314,515
- Issue date Apr 26, 2022
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry for low-precision deep learning
- Patent number 11,275,998
- Issue date Mar 15, 2022
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses, methods, and systems for access synchronization in a s...
- Patent number 11,106,464
- Issue date Aug 31, 2021
- Intel Corporation
- Swagath Venkataramani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delivering data from a range of input devices over a secure path to...
- Patent number 9,390,251
- Issue date Jul 12, 2016
- Intel Corporation
- Sasikanth Avancha
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MATRIX OPERATION OPTIMIZATION MECHANISM
- Publication number 20240427842
- Publication date Dec 26, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS
- Publication number 20240320000
- Publication date Sep 26, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES, METHODS, AND SYSTEMS FOR NEURAL NETWORKS
- Publication number 20240118892
- Publication date Apr 11, 2024
- Intel Corporation
- Swagath VENKATARAMANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MATRIX OPERATION OPTIMIZATION MECHANISM
- Publication number 20230289399
- Publication date Sep 14, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC ARRAY HAVING SUPPORT FOR OUTPUT SPARSITY
- Publication number 20220413803
- Publication date Dec 29, 2022
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS AND LOGIC FOR VECTOR MULTIPLY ADD WITH ZERO SKIPPING
- Publication number 20220326953
- Publication date Oct 13, 2022
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES, METHODS, AND SYSTEMS FOR NEURAL NETWORKS
- Publication number 20220050683
- Publication date Feb 17, 2022
- Intel Corporation
- Swagath VENKATARAMANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES, METHODS, AND SYSTEMS FOR ACCESS SYNCHRONIZATION IN A S...
- Publication number 20210382719
- Publication date Dec 9, 2021
- Intel Corporation
- Swagath VENKATARAMANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MATRIX OPERATION OPTIMIZATION MECHANISM
- Publication number 20210374209
- Publication date Dec 2, 2021
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS AND LOGIC FOR VECTOR MULTIPLY ADD WITH ZERO SKIPPING
- Publication number 20210191724
- Publication date Jun 24, 2021
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS
- Publication number 20210081201
- Publication date Mar 18, 2021
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES, METHODS, AND SYSTEMS FOR NEURAL NETWORKS
- Publication number 20190303743
- Publication date Oct 3, 2019
- Intel Corporation
- Swagath VENKATARAMANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES, METHODS, AND SYSTEMS FOR ACCESS SYNCHRONIZATION IN A S...
- Publication number 20190243651
- Publication date Aug 8, 2019
- Intel Corporation
- Swagath VENKATARAMANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUITRY FOR LOW-PRECISION DEEP LEARNING
- Publication number 20190042939
- Publication date Feb 7, 2019
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELIVERING DATA FROM A RANGE OF INPUT DEVICES OVER A SECURE PATH TO...
- Publication number 20140310799
- Publication date Oct 16, 2014
- Sasikanth Avancha
- G06 - COMPUTING CALCULATING COUNTING

Sasikanth Avancha

Person

Patents Grantslast 30 patents

Matrix operation optimization mechanism

Utilizing structured sparsity in systolic arrays

Apparatuses, methods, and systems for access synchronization in a s...

Instructions and logic for vector multiply add with zero skipping

Matrix operation optimization mechanism

Instructions and logic for vector multiply add with zero skipping

Circuitry for low-precision deep learning

Apparatuses, methods, and systems for access synchronization in a s...

Delivering data from a range of input devices over a secure path to...

Patents Applicationslast 30 patents

MATRIX OPERATION OPTIMIZATION MECHANISM

UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS

APPARATUSES, METHODS, AND SYSTEMS FOR NEURAL NETWORKS

MATRIX OPERATION OPTIMIZATION MECHANISM

SYSTOLIC ARRAY HAVING SUPPORT FOR OUTPUT SPARSITY

INSTRUCTIONS AND LOGIC FOR VECTOR MULTIPLY ADD WITH ZERO SKIPPING

APPARATUSES, METHODS, AND SYSTEMS FOR NEURAL NETWORKS

APPARATUSES, METHODS, AND SYSTEMS FOR ACCESS SYNCHRONIZATION IN A S...

MATRIX OPERATION OPTIMIZATION MECHANISM

INSTRUCTIONS AND LOGIC FOR VECTOR MULTIPLY ADD WITH ZERO SKIPPING

UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS

APPARATUSES, METHODS, AND SYSTEMS FOR NEURAL NETWORKS

APPARATUSES, METHODS, AND SYSTEMS FOR ACCESS SYNCHRONIZATION IN A S...

CIRCUITRY FOR LOW-PRECISION DEEP LEARNING

DELIVERING DATA FROM A RANGE OF INPUT DEVICES OVER A SECURE PATH TO...