Sasikanth Sasi Manipatruni

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-input threshold gate having stacked and folded non-planar cap...
- Patent number 12,171,103
- Issue date Dec 17, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
Information Patent Grant
Method of forming an artificial intelligence processor with three-d...
- Patent number 12,166,011
- Issue date Dec 10, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Grant
Reset mechanism for an adder or a multiplier having paraelectric ma...
- Patent number 12,155,383
- Issue date Nov 26, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area oriented logic synthesis
- Patent number 12,147,747
- Issue date Nov 19, 2024
- Kepler Computing Inc.
- Ikenna Odinaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Iterative monetization of precursor in process development of non-l...
- Patent number 12,147,941
- Issue date Nov 19, 2024
- Kepler Computing Inc.
- Sasikanth Manipatruni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of fabricating pedestal based memory devices using pocket in...
- Patent number 12,142,310
- Issue date Nov 12, 2024
- Kepler Computing Inc.
- Noriyuki Sato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration of ferroelectric memory devices having stacked electrod...
- Patent number 12,137,574
- Issue date Nov 5, 2024
- Kepler Computing Inc.
- Sasikanth Manipatruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus with selectable majority gate and combinational logic gat...
- Patent number 12,126,339
- Issue date Oct 22, 2024
- Kepler Computing Inc.
- Sasikanth Manipatruni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Ripple carry adder with inverted ferroelectric or paraelectric base...
- Patent number 12,118,327
- Issue date Oct 15, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power multiplier with non-linear polar material based reset mec...
- Patent number 12,118,330
- Issue date Oct 15, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ferroelectric capacitor integrated with logic
- Patent number 12,113,097
- Issue date Oct 8, 2024
- Kepler Computing Inc.
- Gaurav Thareja
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory bit-cell with stacked and folded planar capacitors
- Patent number 12,108,609
- Issue date Oct 1, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for conditioning majority or minority gate
- Patent number 12,107,579
- Issue date Oct 1, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Devices with continuous electrode plate and methods of fabrication
- Patent number 12,108,607
- Issue date Oct 1, 2024
- Kepler Computing Inc.
- Noriyuki Sato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory devices with dual encapsulation layers and methods of fabric...
- Patent number 12,108,608
- Issue date Oct 1, 2024
- Kepler Computing Inc.
- Noriyuki Sato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Write disturb mitigation for column multiplexed non-linear polar ma...
- Patent number 12,094,511
- Issue date Sep 17, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Grant
One transistor and N memory element based memory bit-cell having st...
- Patent number 12,096,638
- Issue date Sep 17, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Grant
Rapid thermal annealing (RTA) methodologies for integration of pero...
- Patent number 12,094,923
- Issue date Sep 17, 2024
- Kepler Computing Inc.
- Niloy Mukherjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Majority gate based low power ferroelectric based adder with reset...
- Patent number 12,088,297
- Issue date Sep 10, 2024
- Kepler Computing Inc.
- Sasikanth Manipatruni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-input threshold gate having stacked and folded planar capacit...
- Patent number 12,087,730
- Issue date Sep 10, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Grant
Ferroelectric memory chiplet in a multi-dimensional packaging with...
- Patent number 12,086,410
- Issue date Sep 10, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ferroelectric memory chiplet in a multi-dimensional packaging
- Patent number 12,079,475
- Issue date Sep 3, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pocket integration process for embedded memory
- Patent number 12,069,866
- Issue date Aug 20, 2024
- Kepler Computing Inc.
- Noriyuki Sato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Iterative method of multilayer stack development for device applica...
- Patent number 12,062,584
- Issue date Aug 13, 2024
- Kepler Computing Inc.
- Sasikanth Manipatruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
1TnC memory bit-cell having stacked and folded non-planar capacitors
- Patent number 12,041,785
- Issue date Jul 16, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
Information Patent Grant
Trench capacitors with continuous dielectric layer and methods of f...
- Patent number 12,034,086
- Issue date Jul 9, 2024
- Somilkumar J. Rathi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planar and trench capacitors with hydrogen barrier dielectric for l...
- Patent number 12,029,043
- Issue date Jul 2, 2024
- Kepler Computing Inc.
- Somilkumar J. Rathi
Information Patent Grant
Method and apparatus for heuristic-based power gating of non-CMOS l...
- Patent number 12,026,034
- Issue date Jul 2, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Planar and trench capacitors for logic and memory applications and...
- Patent number 12,022,662
- Issue date Jun 25, 2024
- Kepler Computing Inc.
- Somilkumar J. Rathi
Information Patent Grant
Method and apparatus for managing power in a multi-dimensional pack...
- Patent number 12,019,492
- Issue date Jun 25, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DOPED POLAR LAYERS AND SEMICONDUCTOR DEVICE INCORPORATING SAME
- Publication number 20240421229
- Publication date Dec 19, 2024
- Kepler Computing Inc.
- Ramesh Ramamoorthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING FERROELECTRIC CHIPLET IN A MULTI-DIMENSIONAL PACK...
- Publication number 20240402908
- Publication date Dec 5, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF FORMING A MAJORITY GATE BASED LOW POWER FERROELECTRIC BAS...
- Publication number 20240380403
- Publication date Nov 14, 2024
- Kepler Computing Inc.
- Sasikanth Manipatruni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARE...
- Publication number 20240379143
- Publication date Nov 14, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Application
FERROELECTRIC CAPACITOR INTEGRATED WITH A LOGIC DEVICE
- Publication number 20240379733
- Publication date Nov 14, 2024
- Kepler Computing Inc.
- Gaurav Thareja
- G11 - INFORMATION STORAGE
Information Patent Application
NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARE...
- Publication number 20240379144
- Publication date Nov 14, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF MEMORY DEVICE FABRICATION THROUGH ITERATIVE MULTILAYER ST...
- Publication number 20240347397
- Publication date Oct 17, 2024
- Kepler Computing Inc.
- Sasikanth Manipatruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FERROELECTRIC MEMORY CHIPLET IN A MULTI-DIMENSIONAL PACKAGING WITH...
- Publication number 20240311006
- Publication date Sep 19, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF FABRICATING MEMORY DEVICES INCLUDING B-SITE DOPANTS AND L...
- Publication number 20240276734
- Publication date Aug 15, 2024
- Kepler Computing Inc.
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING STACKED CAPACITORS THROUGH WAFER BONDING
- Publication number 20240274651
- Publication date Aug 15, 2024
- Kepler Computing Inc.
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING CAPACITORS THROUGH WAFER BONDING
- Publication number 20240276735
- Publication date Aug 15, 2024
- Kepler Computing Inc.
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR HIGH DENSITY BIT-CELL
- Publication number 20240257854
- Publication date Aug 1, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Application
ITERATIVE MONETIZATION OF PRECURSOR IN PROCESS DEVELOPMENT OF NON-L...
- Publication number 20240211872
- Publication date Jun 27, 2024
- Kepler Computing Inc.
- Sasikanth Manipatruni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATION OF FERROELECTRIC MEMORY DEVICES HAVING STACKED ELECTROD...
- Publication number 20240099018
- Publication date Mar 21, 2024
- Kepler Computing Inc.
- Sasikanth Manipatruni
- G11 - INFORMATION STORAGE
Information Patent Application
DOPED POLAR LAYERS AND SEMICONDUCTOR DEVICE INCORPORATING SAME
- Publication number 20240088299
- Publication date Mar 14, 2024
- Kepler Computing Inc.
- Ramesh Ramamoorthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING 3D STACKED COMPUTE AND MEMORY WITH COPPER PILLARS
- Publication number 20240047426
- Publication date Feb 8, 2024
- Kepler Computing Inc.
- Sasikanth MANIPATRUNI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-DENSITY LOW VOLTAGE FERROELECTRIC DIFFERENTIAL MEMORY BIT-CELL...
- Publication number 20230420022
- Publication date Dec 28, 2023
- Kepler Computing Inc.
- Sasikanth Manipatruni
- G11 - INFORMATION STORAGE
Information Patent Application
WRITE DISTURB MITIGATION FOR NON-LINEAR POLAR MATERIAL BASED MULTI-...
- Publication number 20230395134
- Publication date Dec 7, 2023
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Application
PEROVSKITE-BASED MAGNETOELECTRIC SPIN-ORBIT LOGIC DEVICES
- Publication number 20230353157
- Publication date Nov 2, 2023
- Tanay A. Gosavi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MAJORITY GATE BASED LOW POWER FERROELECTRIC BASED ADDER WITH RESET...
- Publication number 20230308102
- Publication date Sep 28, 2023
- Kepler Computing, Inc.
- Sasikanth Manipatruni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAIN COUPLED NON-LINEAR POLAR MATERIAL BASED CAPACITORS FOR MEMORY...
- Publication number 20230301113
- Publication date Sep 21, 2023
- Kepler Computing Inc.
- Noriyuki Sato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING A PEROVSKITE-MATERIAL BASED PLANAR CAPACITOR...
- Publication number 20230298905
- Publication date Sep 21, 2023
- Kepler Computing Inc.
- Niloy Mukherjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PILLAR CAPACITOR AND METHOD OF FABRICATING SUCH
- Publication number 20230284455
- Publication date Sep 7, 2023
- Kepler Computing Inc.
- Gaurav Thareja
- G11 - INFORMATION STORAGE
Information Patent Application
ONE TRANSISTOR AND N MEMORY ELEMENT BASED MEMORY BIT-CELL HAVING ST...
- Publication number 20230284456
- Publication date Sep 7, 2023
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ASYNCHRONOUS CARRY-RIPPLE ADDER WITH MAJORITY OR MINORITY GATES
- Publication number 20230251828
- Publication date Aug 10, 2023
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF FABRICATING A PEROVSKITE-MATERIAL BASED TRENCH CAPACITOR...
- Publication number 20230246064
- Publication date Aug 3, 2023
- Kepler Computing Inc.
- Niloy Mukherjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RAPID THERMAL ANNEALING (RTA) METHODOLOGIES FOR INTEGRATION OF PERO...
- Publication number 20230246063
- Publication date Aug 3, 2023
- Kepler Computing Inc.
- Niloy Mukherjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RAPID THERMAL ANNEALING (RTA) METHODOLOGIES FOR INTEGRATION OF PERO...
- Publication number 20230246062
- Publication date Aug 3, 2023
- Kepler Computing Inc.
- Niloy Mukherjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MANGANESE-DOPED PEROVSKITE LAYERS AND SEMICONDUCTOR DEVICE INCORPOR...
- Publication number 20230231055
- Publication date Jul 20, 2023
- Kepler Computing Inc.
- Ramesh Ramamoorthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ASYNCHRONOUS CONSENSUS CIRCUIT WITH STACKED LINEAR OR PARAELECTRIC...
- Publication number 20230223936
- Publication date Jul 13, 2023
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING

Sasikanth Sasi Manipatruni

Person

Patents Grantslast 30 patents

Multi-input threshold gate having stacked and folded non-planar cap...

Method of forming an artificial intelligence processor with three-d...

Reset mechanism for an adder or a multiplier having paraelectric ma...

Area oriented logic synthesis

Iterative monetization of precursor in process development of non-l...

Method of fabricating pedestal based memory devices using pocket in...

Integration of ferroelectric memory devices having stacked electrod...

Apparatus with selectable majority gate and combinational logic gat...

Ripple carry adder with inverted ferroelectric or paraelectric base...

Low power multiplier with non-linear polar material based reset mec...

Ferroelectric capacitor integrated with logic

Memory bit-cell with stacked and folded planar capacitors

Method for conditioning majority or minority gate

Devices with continuous electrode plate and methods of fabrication

Memory devices with dual encapsulation layers and methods of fabric...

Write disturb mitigation for column multiplexed non-linear polar ma...

One transistor and N memory element based memory bit-cell having st...

Rapid thermal annealing (RTA) methodologies for integration of pero...

Majority gate based low power ferroelectric based adder with reset...

Multi-input threshold gate having stacked and folded planar capacit...

Ferroelectric memory chiplet in a multi-dimensional packaging with...

Ferroelectric memory chiplet in a multi-dimensional packaging

Pocket integration process for embedded memory

Iterative method of multilayer stack development for device applica...

1TnC memory bit-cell having stacked and folded non-planar capacitors

Trench capacitors with continuous dielectric layer and methods of f...

Planar and trench capacitors with hydrogen barrier dielectric for l...

Method and apparatus for heuristic-based power gating of non-CMOS l...

Planar and trench capacitors for logic and memory applications and...

Method and apparatus for managing power in a multi-dimensional pack...

Patents Applicationslast 30 patents

DOPED POLAR LAYERS AND SEMICONDUCTOR DEVICE INCORPORATING SAME

METHOD OF FORMING FERROELECTRIC CHIPLET IN A MULTI-DIMENSIONAL PACK...

METHOD OF FORMING A MAJORITY GATE BASED LOW POWER FERROELECTRIC BAS...

NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARE...

FERROELECTRIC CAPACITOR INTEGRATED WITH A LOGIC DEVICE

NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARE...

METHOD OF MEMORY DEVICE FABRICATION THROUGH ITERATIVE MULTILAYER ST...

FERROELECTRIC MEMORY CHIPLET IN A MULTI-DIMENSIONAL PACKAGING WITH...

METHOD OF FABRICATING MEMORY DEVICES INCLUDING B-SITE DOPANTS AND L...

METHOD OF FORMING STACKED CAPACITORS THROUGH WAFER BONDING

METHOD OF FORMING CAPACITORS THROUGH WAFER BONDING

NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR HIGH DENSITY BIT-CELL

ITERATIVE MONETIZATION OF PRECURSOR IN PROCESS DEVELOPMENT OF NON-L...

INTEGRATION OF FERROELECTRIC MEMORY DEVICES HAVING STACKED ELECTROD...

DOPED POLAR LAYERS AND SEMICONDUCTOR DEVICE INCORPORATING SAME

METHOD OF FORMING 3D STACKED COMPUTE AND MEMORY WITH COPPER PILLARS

HIGH-DENSITY LOW VOLTAGE FERROELECTRIC DIFFERENTIAL MEMORY BIT-CELL...

WRITE DISTURB MITIGATION FOR NON-LINEAR POLAR MATERIAL BASED MULTI-...

PEROVSKITE-BASED MAGNETOELECTRIC SPIN-ORBIT LOGIC DEVICES

MAJORITY GATE BASED LOW POWER FERROELECTRIC BASED ADDER WITH RESET...

DRAIN COUPLED NON-LINEAR POLAR MATERIAL BASED CAPACITORS FOR MEMORY...

METHOD OF FABRICATING A PEROVSKITE-MATERIAL BASED PLANAR CAPACITOR...

PILLAR CAPACITOR AND METHOD OF FABRICATING SUCH

ONE TRANSISTOR AND N MEMORY ELEMENT BASED MEMORY BIT-CELL HAVING ST...

ASYNCHRONOUS CARRY-RIPPLE ADDER WITH MAJORITY OR MINORITY GATES

METHOD OF FABRICATING A PEROVSKITE-MATERIAL BASED TRENCH CAPACITOR...

RAPID THERMAL ANNEALING (RTA) METHODOLOGIES FOR INTEGRATION OF PERO...

RAPID THERMAL ANNEALING (RTA) METHODOLOGIES FOR INTEGRATION OF PERO...

MANGANESE-DOPED PEROVSKITE LAYERS AND SEMICONDUCTOR DEVICE INCORPOR...

ASYNCHRONOUS CONSENSUS CIRCUIT WITH STACKED LINEAR OR PARAELECTRIC...