Satish Damaraju

Person

El Dorado Hills, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Controlling power delivery to a processor via a bypass
- Patent number 11,687,135
- Issue date Jun 27, 2023
- Tahoe Research, LTD.
- Sanjeev S. Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multibit vectored sequential with scan
- Patent number 11,442,103
- Issue date Sep 13, 2022
- Intel Corporation
- Amit Agarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low-power single-edge triggered flip-flop, and time borrowing inter...
- Patent number 11,398,814
- Issue date Jul 26, 2022
- Intel Corporation
- Steven Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling power delivery to a processor via a bypass
- Patent number 11,157,052
- Issue date Oct 26, 2021
- Intel Corporation
- Sanjeev S. Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multibit vectored sequential with scan
- Patent number 11,009,549
- Issue date May 18, 2021
- Intel Corporation
- Amit Agarwal
- G01 - MEASURING TESTING
Information Patent Grant
Multibit vectored sequential with scan
- Patent number 10,473,718
- Issue date Nov 12, 2019
- Intel Corporation
- Amit Agarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Controlling power delivery to a processor via a bypass
- Patent number 10,429,913
- Issue date Oct 1, 2019
- Intel Corporation
- Sanjeev S. Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling power delivery to a processor via a bypass
- Patent number 10,409,346
- Issue date Sep 10, 2019
- Intel Corporation
- Sanjeev S. Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling power delivery to a processor via a bypass
- Patent number 10,146,283
- Issue date Dec 4, 2018
- Intel Corporation
- Sanjeev S. Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling power delivery to a processor via a bypass
- Patent number 9,823,719
- Issue date Nov 21, 2017
- Intel Corporation
- Sanjeev S. Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared function multi-ported ROM apparatus and method
- Patent number 9,336,008
- Issue date May 10, 2016
- Intel Corporation
- Satish K. Damaraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic error handling using parity and redundant rows
- Patent number 9,075,741
- Issue date Jul 7, 2015
- Intel Corporation
- Altug Koker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method, apparatus, and system for energy efficiency and energy cons...
- Patent number 8,713,256
- Issue date Apr 29, 2014
- Intel Corporation
- Inder M. Sodhi
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Increasing memory bandwidth in processor-based systems
- Patent number 8,448,010
- Issue date May 21, 2013
- Intel Corporation
- Satish K. Damaraju
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for reducing power consumption in a device using...
- Patent number 8,356,202
- Issue date Jan 15, 2013
- Intel Corporation
- Satish Damaraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell write
- Patent number 8,345,491
- Issue date Jan 1, 2013
- Intel Corporation
- Satish K. Damaraju
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell write
- Patent number 8,050,116
- Issue date Nov 1, 2011
- Intel Corporation
- Satish K. Damaraju
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit technique to reduce leakage during reduced power mode
- Patent number 7,805,619
- Issue date Sep 28, 2010
- Intel Corporation
- John R. Cherukuri
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power-performance modulation in caches using a smart least recently...
- Patent number 7,689,772
- Issue date Mar 30, 2010
- Intel Corporation
- Satish Damaraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing power consumption in a sequential cache
- Patent number 7,457,917
- Issue date Nov 25, 2008
- Intel Corporation
- Satish Damaraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Look ahead LRU array update scheme to minimize clobber in sequentia...
- Patent number 7,155,574
- Issue date Dec 26, 2006
- Intel Corporation
- Peter J. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power cache architecture
- Patent number 7,136,984
- Issue date Nov 14, 2006
- Intel Corporation
- Subramaniam J. Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power delay controlled zero sensitive sense amplifier
- Patent number 7,130,236
- Issue date Oct 31, 2006
- Intel Corporation
- Iqbal Rajwani
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT ASSEMBLIES HAVING INTERCONNECTION BRIDGES SPANNI...
- Publication number 20230387074
- Publication date Nov 30, 2023
- Intel Corporation
- Debendra Mallik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SCALABLE PACKAGE ARCHITECTURE USING RETICLE STITCHING AND PHOTONICS...
- Publication number 20230352464
- Publication date Nov 2, 2023
- Intel Corporation
- Satish Damaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIPLET ARCHITECTURE FOR LATE BIND SKU FUNGIBILITY
- Publication number 20230305978
- Publication date Sep 28, 2023
- Intel Corporation
- Mark C. Davis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULATING DIE ROTATION TO MINIMIZE AREA OVERHEAD OF RETICLE STITCH...
- Publication number 20230205094
- Publication date Jun 29, 2023
- Intel Corporation
- Scott Siers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH SPEED MEMORY SYSTEM INTEGRATION
- Publication number 20220197806
- Publication date Jun 23, 2022
- Intel Corporation
- Shigeki TOMISHIMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlling Power Delivery To A Processor Via A Bypass
- Publication number 20220004237
- Publication date Jan 6, 2022
- Intel Corporation
- Sanjeev S. Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-POWER SINGLE-EDGE TRIGGERED FLIP-FLOP, AND TIME BORROWING INTER...
- Publication number 20210281250
- Publication date Sep 9, 2021
- Intel Corporation
- Steven Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIBIT VECTORED SEQUENTIAL WITH SCAN
- Publication number 20210263100
- Publication date Aug 26, 2021
- Intel Corporation
- Amit Agarwal
- G01 - MEASURING TESTING
Information Patent Application
MULTIBIT VECTORED SEQUENTIAL WITH SCAN
- Publication number 20200150179
- Publication date May 14, 2020
- Intel Corporation
- Amit Agarwal
- G01 - MEASURING TESTING
Information Patent Application
Controlling Power Delivery To A Processor Via A Bypass
- Publication number 20200019221
- Publication date Jan 16, 2020
- Intel Corporation
- Sanjeev S. Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIBIT VECTORED SEQUENTIAL WITH SCAN
- Publication number 20190187208
- Publication date Jun 20, 2019
- Intel Corporation
- Amit Agarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Controlling Power Delivery To A Processor Via A Bypass
- Publication number 20180341305
- Publication date Nov 29, 2018
- Intel Corporation
- Sanjeev S. Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlling Power Delivery To A Processor Via A Bypass
- Publication number 20180341306
- Publication date Nov 29, 2018
- Intel Corporation
- Sanjeev S. Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Execution Unit with Selective Instruction Pipeline Bypass
- Publication number 20180203694
- Publication date Jul 19, 2018
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlling Power Delivery To A Processor Via A Bypass
- Publication number 20180059751
- Publication date Mar 1, 2018
- Intel Corporation
- Sanjeev S. Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlling Power Delivery To A Processor Via A Bypass
- Publication number 20140359311
- Publication date Dec 4, 2014
- Sanjeev S. Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC ERROR HANDLING USING PARITY AND REDUNDANT ROWS
- Publication number 20130159820
- Publication date Jun 20, 2013
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED FUNCTION MULTI-PORTED ROM APPARATUS AND METHOD
- Publication number 20120198208
- Publication date Aug 2, 2012
- Satish K. Damaraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONS...
- Publication number 20120159074
- Publication date Jun 21, 2012
- Inder M. Sodhi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CELL WRITE
- Publication number 20120039135
- Publication date Feb 16, 2012
- Satish K. Damaraju
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY HAVING EXTENDED WRITE OPERATION
- Publication number 20110149661
- Publication date Jun 23, 2011
- Iqbal R. Rajwani
- G11 - INFORMATION STORAGE
Information Patent Application
Increasing Memory Bandwidth in Processor-Based Systems
- Publication number 20110078485
- Publication date Mar 31, 2011
- Satish K. Damaraju
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL WRITE
- Publication number 20110069566
- Publication date Mar 24, 2011
- Satish K. Damaraju
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A DEVICE USING...
- Publication number 20090249041
- Publication date Oct 1, 2009
- Intel Corporation
- Satish Damaraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power-performance modulation in caches using a smart least recently...
- Publication number 20070260818
- Publication date Nov 8, 2007
- Satish Damaraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit technique to reduce leakage during reduced power mode
- Publication number 20070236256
- Publication date Oct 11, 2007
- John R. Cherukuri
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Look ahead LRU array update scheme to minimize clobber in sequentia...
- Publication number 20060218351
- Publication date Sep 28, 2006
- Peter J. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER DELAY CONTROLLED ZERO SENSITIVE SENSE AMPLIFIER
- Publication number 20060209606
- Publication date Sep 21, 2006
- Iqbal Rajwani
- G11 - INFORMATION STORAGE
Information Patent Application
Reducing power consumption in a sequential cache
- Publication number 20060143382
- Publication date Jun 29, 2006
- Satish Damaraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low power cache architecture
- Publication number 20050097277
- Publication date May 5, 2005
- Subramaniam J. Maiyuran
- G06 - COMPUTING CALCULATING COUNTING

Satish Damaraju

Person

Patents Grantslast 30 patents

Controlling power delivery to a processor via a bypass

Multibit vectored sequential with scan

Low-power single-edge triggered flip-flop, and time borrowing inter...

Controlling power delivery to a processor via a bypass

Multibit vectored sequential with scan

Multibit vectored sequential with scan

Controlling power delivery to a processor via a bypass

Controlling power delivery to a processor via a bypass

Controlling power delivery to a processor via a bypass

Controlling power delivery to a processor via a bypass

Shared function multi-ported ROM apparatus and method

Dynamic error handling using parity and redundant rows

Method, apparatus, and system for energy efficiency and energy cons...

Increasing memory bandwidth in processor-based systems

System and method for reducing power consumption in a device using...

Memory cell write

Memory cell write

Circuit technique to reduce leakage during reduced power mode

Power-performance modulation in caches using a smart least recently...

Reducing power consumption in a sequential cache

Look ahead LRU array update scheme to minimize clobber in sequentia...

Low power cache architecture

Low power delay controlled zero sensitive sense amplifier

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT ASSEMBLIES HAVING INTERCONNECTION BRIDGES SPANNI...

SCALABLE PACKAGE ARCHITECTURE USING RETICLE STITCHING AND PHOTONICS...

CHIPLET ARCHITECTURE FOR LATE BIND SKU FUNGIBILITY

SIMULATING DIE ROTATION TO MINIMIZE AREA OVERHEAD OF RETICLE STITCH...

HIGH SPEED MEMORY SYSTEM INTEGRATION

Controlling Power Delivery To A Processor Via A Bypass

LOW-POWER SINGLE-EDGE TRIGGERED FLIP-FLOP, AND TIME BORROWING INTER...

MULTIBIT VECTORED SEQUENTIAL WITH SCAN

MULTIBIT VECTORED SEQUENTIAL WITH SCAN

Controlling Power Delivery To A Processor Via A Bypass

MULTIBIT VECTORED SEQUENTIAL WITH SCAN

Controlling Power Delivery To A Processor Via A Bypass

Controlling Power Delivery To A Processor Via A Bypass

Execution Unit with Selective Instruction Pipeline Bypass

Controlling Power Delivery To A Processor Via A Bypass

Controlling Power Delivery To A Processor Via A Bypass

DYNAMIC ERROR HANDLING USING PARITY AND REDUNDANT ROWS

SHARED FUNCTION MULTI-PORTED ROM APPARATUS AND METHOD

METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONS...

MEMORY CELL WRITE

MEMORY ARRAY HAVING EXTENDED WRITE OPERATION

Increasing Memory Bandwidth in Processor-Based Systems

MEMORY CELL WRITE

SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A DEVICE USING...

Power-performance modulation in caches using a smart least recently...

Circuit technique to reduce leakage during reduced power mode

Look ahead LRU array update scheme to minimize clobber in sequentia...

LOW POWER DELAY CONTROLLED ZERO SENSITIVE SENSE AMPLIFIER

Reducing power consumption in a sequential cache

Low power cache architecture