Satish R. Ganesan

Person

Mountain View, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit arrangement for profiling a programmable processor connecte...
- Patent number 7,840,781
- Issue date Nov 23, 2010
- Xilinx, Inc.
- Sivakumar Velusamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Event-driven simulation of IP using third party event-driven simula...
- Patent number 7,721,090
- Issue date May 18, 2010
- Xilinx, Inc.
- Kumar Deepak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for function acceleration using custom instructions
- Patent number 7,676,661
- Issue date Mar 9, 2010
- Xilinx, Inc.
- Sundararajarao Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Framework for cycle accurate simulation
- Patent number 7,606,694
- Issue date Oct 20, 2009
- Xilinx, Inc.
- Jorge Ernesto Carrillo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Auto-generation and placement of arbitration logic in a multi-maste...
- Patent number 7,426,709
- Issue date Sep 16, 2008
- Xilinx, Inc.
- Satish R. Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for fast linked processor in a system on a chip (...
- Patent number 7,340,585
- Issue date Mar 4, 2008
- Xilinx, Inc.
- Satish R. Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for designing a multiprocessor
- Patent number 7,310,594
- Issue date Dec 18, 2007
- Xilinx, Inc.
- Satish R. Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing self-implementing hardware-softw...
- Patent number 7,243,330
- Issue date Jul 10, 2007
- Xilinx, Inc.
- Satish R. Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating fast logic simulation models for a PLD design description
- Patent number 7,131,091
- Issue date Oct 31, 2006
- Xilinx, Inc.
- Satish R. Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Softpal implementation and mapping technology for FPGAs with dedica...
- Patent number 7,111,273
- Issue date Sep 19, 2006
- Xilinx, Inc.
- Satish R. Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PLD configurable logic block enabling the rapid calculation of sum-...
- Patent number 6,833,730
- Issue date Dec 21, 2004
- Xilinx, Inc.
- Satish R. Ganesan
- G06 - COMPUTING CALCULATING COUNTING

Satish R. Ganesan

Person

Patents Grantslast 30 patents

Circuit arrangement for profiling a programmable processor connecte...

Event-driven simulation of IP using third party event-driven simula...

Method and system for function acceleration using custom instructions

Framework for cycle accurate simulation

Auto-generation and placement of arbitration logic in a multi-maste...

Method and system for fast linked processor in a system on a chip (...

Method and system for designing a multiprocessor

Method and apparatus for providing self-implementing hardware-softw...

Generating fast logic simulation models for a PLD design description

Softpal implementation and mapping technology for FPGAs with dedica...

PLD configurable logic block enabling the rapid calculation of sum-...