Satish Venkatesan

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Subsystem-based SoC integration
- Patent number 10,860,762
- Issue date Dec 8, 2020
- Intel Corpration
- Robert P. Adler
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FPGA BASED PLATFORM FOR POST-SILICON VALIDATION OF CHIPLETS
- Publication number 20230401130
- Publication date Dec 14, 2023
- Intel Corporation
- Rakesh Mehta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUBSYSTEM-BASED SOC INTEGRATION
- Publication number 20190340313
- Publication date Nov 7, 2019
- Intel Corporation
- Robert P. Adler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DECODE INFORMATION LIBRARY
- Publication number 20160179161
- Publication date Jun 23, 2016
- Robert P. Adler
- G06 - COMPUTING CALCULATING COUNTING