Satoru Nunokawa

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Hino-shi, JP

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Patents Grantslast 30 patents

Information Patent Grant
Digital PLL circuit and method of controlling the same
- Patent number 8,248,122
- Issue date Aug 21, 2012
- Kabushiki Kaisha Toshiba
- Taro Shibagaki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Unit for predicting malfunction of an apparatus
- Patent number 8,140,916
- Issue date Mar 20, 2012
- Kabushiki Kaisha Toshiba
- Taro Shibagaki
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
UNIT FOR PREDICTING MALFUNCTION OF AN APPARATUS
- Publication number 20110113289
- Publication date May 12, 2011
- Taro SHIBAGAKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL PLL CIRCUIT AND METHOD OF CONTROLLING THE SAME
- Publication number 20110109353
- Publication date May 12, 2011
- Taro SHIBAGAKI
- H03 - BASIC ELECTRONIC CIRCUITRY