Satoru Ooshima

Person

Tokyo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Communication system using transmit/receive slot antennas for near...
- Patent number 8,121,544
- Issue date Feb 21, 2012
- Sony Corporation
- Tatsuo Shimizu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Signal processing device
- Patent number 7,956,660
- Issue date Jun 7, 2011
- Sony Corporation
- Satoru Ooshima
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Wireless communication apparatus, wireless network system, communic...
- Patent number 7,801,574
- Issue date Sep 21, 2010
- Sony Corporation
- Satoshi Ueda
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase error determination method and digital phase-locked loop system
- Patent number 7,730,366
- Issue date Jun 1, 2010
- Sony Corporation
- Shinobu Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase error determination method and digital phase-locked loop system
- Patent number 7,469,367
- Issue date Dec 23, 2008
- Sony Corporation
- Shinobu Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital PLL device
- Patent number 7,342,986
- Issue date Mar 11, 2008
- Sony Corporation
- Shinobu Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase error determination method and digital phase-locked loop system
- Patent number 7,315,968
- Issue date Jan 1, 2008
- Sony Corporation
- Shinobu Nakamura
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
COMMUNICATION SYSTEM AND ANTENNA APPARATUS
- Publication number 20090273418
- Publication date Nov 5, 2009
- SONY CORPORATION
- Tatsuo Shimizu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIGNAL PROCESSING DEVICE
- Publication number 20090243685
- Publication date Oct 1, 2009
- SONY CORPORATION
- Satoru OOSHIMA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Phase error determination method and digital phase-locked loop system
- Publication number 20070094549
- Publication date Apr 26, 2007
- Sony Corporation
- Shinobu Nakamura
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Phase error determination method and digital phase-locked loop system
- Publication number 20070088992
- Publication date Apr 19, 2007
- Sony Corporation
- Shinobu Nakamura
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Wireless communication apparatus, wireless network system, communic...
- Publication number 20060270437
- Publication date Nov 30, 2006
- SONY CORPORATION
- Satoshi Ueda
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Wireless communication apparatus, communication system, communicati...
- Publication number 20060193287
- Publication date Aug 31, 2006
- Satoru Ooshima
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Phase error determination method and digital phase-locked loop system
- Publication number 20050022076
- Publication date Jan 27, 2005
- Shinobu Nakamura
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Digital PLL device
- Publication number 20040264623
- Publication date Dec 30, 2004
- Shinobu Nakamura
- H03 - BASIC ELECTRONIC CIRCUITRY

Satoru Ooshima

Person

Patents Grantslast 30 patents

Communication system using transmit/receive slot antennas for near...

Signal processing device

Wireless communication apparatus, wireless network system, communic...

Phase error determination method and digital phase-locked loop system

Phase error determination method and digital phase-locked loop system

Digital PLL device

Phase error determination method and digital phase-locked loop system

Patents Applicationslast 30 patents

COMMUNICATION SYSTEM AND ANTENNA APPARATUS

SIGNAL PROCESSING DEVICE

Phase error determination method and digital phase-locked loop system

Phase error determination method and digital phase-locked loop system

Wireless communication apparatus, wireless network system, communic...

Wireless communication apparatus, communication system, communicati...

Phase error determination method and digital phase-locked loop system

Digital PLL device