Satoru Sueki

Person

Tokyo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Method of manufacturing layered chip package
- Patent number 8,513,034
- Issue date Aug 20, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- G11 - INFORMATION STORAGE
Information Patent Grant
Layered chip package with wiring on the side surfaces
- Patent number 8,324,741
- Issue date Dec 4, 2012
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package with heat sink
- Patent number 8,154,116
- Issue date Apr 10, 2012
- HeadwayTechnologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package
- Patent number 8,134,229
- Issue date Mar 13, 2012
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package with wiring on the side surfaces
- Patent number 7,968,374
- Issue date Jun 28, 2011
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 7,964,976
- Issue date Jun 21, 2011
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- G11 - INFORMATION STORAGE
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 7,868,442
- Issue date Jan 11, 2011
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing layered chip package
- Patent number 7,863,095
- Issue date Jan 4, 2011
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 7,846,772
- Issue date Dec 7, 2010
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing layered chip package
- Patent number 7,767,494
- Issue date Aug 3, 2010
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 7,745,259
- Issue date Jun 29, 2010
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package that implements memory device
- Patent number 7,557,439
- Issue date Jul 7, 2009
- TDK Corporation
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Layered chip package with wiring on the side surfaces
- Publication number 20110221073
- Publication date Sep 15, 2011
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of manufacturing layered chip package
- Publication number 20110201137
- Publication date Aug 18, 2011
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- G11 - INFORMATION STORAGE
Information Patent Application
Layered chip package
- Publication number 20100327464
- Publication date Dec 30, 2010
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of manufacturing layered chip package
- Publication number 20100304531
- Publication date Dec 2, 2010
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layered chip package and method of manufacturing same
- Publication number 20100200977
- Publication date Aug 12, 2010
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layered chip package with heat sink
- Publication number 20100109137
- Publication date May 6, 2010
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layered chip package and method of manufacturing same
- Publication number 20100044879
- Publication date Feb 25, 2010
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- G11 - INFORMATION STORAGE
Information Patent Application
Method of manufacturing layered chip package
- Publication number 20090325345
- Publication date Dec 31, 2009
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layered chip package and method of manufacturing same
- Publication number 20090321956
- Publication date Dec 31, 2009
- TDK Corporation
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layered chip package and method of manufacturing same
- Publication number 20090321957
- Publication date Dec 31, 2009
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layered chip package and method of manufacturing same
- Publication number 20090315189
- Publication date Dec 24, 2009
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS

Satoru Sueki

Person

Patents Grantslast 30 patents

Method of manufacturing layered chip package

Layered chip package with wiring on the side surfaces

Layered chip package with heat sink

Layered chip package

Layered chip package with wiring on the side surfaces

Layered chip package and method of manufacturing same

Layered chip package and method of manufacturing same

Method of manufacturing layered chip package

Layered chip package and method of manufacturing same

Method of manufacturing layered chip package

Layered chip package and method of manufacturing same

Layered chip package that implements memory device

Patents Applicationslast 30 patents

Layered chip package with wiring on the side surfaces

Method of manufacturing layered chip package

Layered chip package

Method of manufacturing layered chip package

Layered chip package and method of manufacturing same

Layered chip package with heat sink

Layered chip package and method of manufacturing same

Method of manufacturing layered chip package

Layered chip package and method of manufacturing same

Layered chip package and method of manufacturing same

Layered chip package and method of manufacturing same