Satoru Tamada

Person

Kamakura-city, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Enable/disable of memory chunks during memory access
- Patent number 9,536,582
- Issue date Jan 3, 2017
- Micron Technology, Inc.
- Toru Tanzawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Enable/disable of memory chunks during memory access
- Patent number 9,064,578
- Issue date Jun 23, 2015
- Micron Technology, Inc.
- Toru Tanzawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array with inverted data-lines pairs
- Patent number 8,576,627
- Issue date Nov 5, 2013
- Micron Technology, Inc.
- Satoru Tamada
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi level inhibit scheme
- Patent number 8,422,297
- Issue date Apr 16, 2013
- Micron Technology, Inc.
- Satoru Tamada
- G11 - INFORMATION STORAGE
Information Patent Grant
Small unit internal verify read in a memory device
- Patent number 8,243,538
- Issue date Aug 14, 2012
- Micron Technology, Inc.
- Tetsuji Manabe
- G11 - INFORMATION STORAGE
Information Patent Grant
Small unit internal verify read in a memory device
- Patent number 8,077,532
- Issue date Dec 13, 2011
- Micron Technology, Inc.
- Tetsuji Manabe
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array with inverted data-line pairs
- Patent number 7,983,085
- Issue date Jul 19, 2011
- Micron Technology, Inc.
- Satoru Tamada
- G11 - INFORMATION STORAGE
Information Patent Grant
Divided bitline flash memory array with local sense and signal tran...
- Patent number 7,983,091
- Issue date Jul 19, 2011
- Intel Corporation
- Satoru Tamada
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and devices including memory resistant to program disturb a...
- Patent number 7,965,548
- Issue date Jun 21, 2011
- Micron Technology, Inc.
- Satoru Tamada
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi level inhibit scheme
- Patent number 7,864,585
- Issue date Jan 4, 2011
- Micron Technology, Inc.
- Satoru Tamada
- G11 - INFORMATION STORAGE
Information Patent Grant
Boosting seed voltage for a memory device
- Patent number 7,835,187
- Issue date Nov 16, 2010
- Intel Corporation
- Satoru Tamada
- G11 - INFORMATION STORAGE
Information Patent Grant
System and devices including memory resistant to program disturb an...
- Patent number 7,755,939
- Issue date Jul 13, 2010
- Micron Technology, Inc.
- Satoru Tamada
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ENABLE/DISABLE OF MEMORY CHUNKS DURING MEMORY ACCESS
- Publication number 20150262636
- Publication date Sep 17, 2015
- Micron Technology, Inc.
- Toru Tanzawa
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS INVOLVING ACCESSING MEMORY CELLS
- Publication number 20140169098
- Publication date Jun 19, 2014
- Micron Technology, Inc.
- Toru Tanzawa
- G11 - INFORMATION STORAGE
Information Patent Application
SMALL UNIT INTERNAL VERIFY READ IN A MEMORY DEVICE
- Publication number 20120063226
- Publication date Mar 15, 2012
- Micron Technology, Inc.
- Tetsuji Manabe
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY WITH INVERTED DATA-LINES PAIRS
- Publication number 20110267882
- Publication date Nov 3, 2011
- Micron Technology, Inc.
- Satoru Tamada
- G11 - INFORMATION STORAGE
Information Patent Application
SMALL UNIT INTERNAL VERIFY READ IN A MEMORY DEVICE
- Publication number 20110051523
- Publication date Mar 3, 2011
- Micron Technology, Inc.
- Tetsuji Manabe
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY WITH INVERTED DATA-LINE PAIRS
- Publication number 20100202201
- Publication date Aug 12, 2010
- Micron Technology, Inc.
- Satoru Tamada
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Devices Including Memory Resistant to Program Disturb a...
- Publication number 20100149866
- Publication date Jun 17, 2010
- Micron Technology, Inc.
- Satoru Tamada
- G11 - INFORMATION STORAGE
Information Patent Application
BOOSTING SEED VOLTAGE FOR A MEMORY DEVICE
- Publication number 20100110795
- Publication date May 6, 2010
- Satoru Tamada
- G11 - INFORMATION STORAGE
Information Patent Application
REDUNDANCY FOR CODE IN ROM
- Publication number 20090248955
- Publication date Oct 1, 2009
- Satoru Tamada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI LEVEL INHIBIT SCHEME
- Publication number 20090207657
- Publication date Aug 20, 2009
- Satoru Tamada
- G11 - INFORMATION STORAGE
Information Patent Application
System and Devices Including Memory Resistant to Program Disturb an...
- Publication number 20090180316
- Publication date Jul 16, 2009
- Micron Technology, Inc.
- Satoru Tamada
- G11 - INFORMATION STORAGE
Information Patent Application
DIVIDED BITLINE FLASH MEMORY ARRAY WITH LOCAL SENSE AND SIGNAL TRAN...
- Publication number 20090119446
- Publication date May 7, 2009
- Intel Corporation
- Satoru Tamada
- G11 - INFORMATION STORAGE

Satoru Tamada

Person

Patents Grantslast 30 patents

Enable/disable of memory chunks during memory access

Enable/disable of memory chunks during memory access

Memory array with inverted data-lines pairs

Multi level inhibit scheme

Small unit internal verify read in a memory device

Small unit internal verify read in a memory device

Memory array with inverted data-line pairs

Divided bitline flash memory array with local sense and signal tran...

Systems and devices including memory resistant to program disturb a...

Multi level inhibit scheme

Boosting seed voltage for a memory device

System and devices including memory resistant to program disturb an...

Patents Applicationslast 30 patents

ENABLE/DISABLE OF MEMORY CHUNKS DURING MEMORY ACCESS

APPARATUSES AND METHODS INVOLVING ACCESSING MEMORY CELLS

SMALL UNIT INTERNAL VERIFY READ IN A MEMORY DEVICE

MEMORY ARRAY WITH INVERTED DATA-LINES PAIRS

SMALL UNIT INTERNAL VERIFY READ IN A MEMORY DEVICE

MEMORY ARRAY WITH INVERTED DATA-LINE PAIRS

Systems and Devices Including Memory Resistant to Program Disturb a...

BOOSTING SEED VOLTAGE FOR A MEMORY DEVICE

REDUNDANCY FOR CODE IN ROM

MULTI LEVEL INHIBIT SCHEME

System and Devices Including Memory Resistant to Program Disturb an...

DIVIDED BITLINE FLASH MEMORY ARRAY WITH LOCAL SENSE AND SIGNAL TRAN...