Satoshi Torii

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method for a memory array with shallow trench isolati...
- Patent number 8,507,971
- Issue date Aug 13, 2013
- Spansion LLC
- Satoshi Torii
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device with barrier layer
- Patent number 7,816,724
- Issue date Oct 19, 2010
- Spansion LLC
- Youseok Suh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and architecture for fast flash memory programming
- Patent number 7,764,546
- Issue date Jul 27, 2010
- Spansion LLC
- Satoshi Torii
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple dual bit memory integrated circuit system
- Patent number 7,692,236
- Issue date Apr 6, 2010
- Spansion LLC
- Michael Brennan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
P-channel NAND in isolated N-well
- Patent number 7,671,403
- Issue date Mar 2, 2010
- Spansion LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and architecture for fast flash memory programming
- Patent number 7,505,328
- Issue date Mar 17, 2009
- Spansion LLC
- Satoshi Torii
- G11 - INFORMATION STORAGE
Information Patent Grant
SONOS memory with inversion bit-lines
- Patent number 7,501,677
- Issue date Mar 10, 2009
- Spansion LLC
- Hidehiko Shiraiwa
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for a memory array with shallow trench isolati...
- Patent number 7,423,312
- Issue date Sep 9, 2008
- Spansion LLC
- Satoshi Torii
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating flash memory devices
- Patent number 7,416,940
- Issue date Aug 26, 2008
- Spansion LLC
- Satoshi Torii
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recessed channel with separated ONO memory device
- Patent number 7,394,125
- Issue date Jul 1, 2008
- FASL LLC
- Jaeyong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation method of an array source line in NAND flash memory
- Patent number 7,238,569
- Issue date Jul 3, 2007
- Spansion LLC
- Satoshi Torii
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Aluminum oxide as liner or cover layer to spacers in memory device
- Patent number 7,196,008
- Issue date Mar 27, 2007
- Spansion LLC
- Hidehiko Shiraiwa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for erasing a memory cell
- Patent number 7,167,398
- Issue date Jan 23, 2007
- Spansion LLC
- Zhizheng Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
SONOS memory with inversion bit-lines
- Patent number 7,151,293
- Issue date Dec 19, 2006
- Spansion, LLC
- Hidehiko Shiraiwa
- G11 - INFORMATION STORAGE
Information Patent Grant
Quad bit using hot-hole erase for CBD control
- Patent number 7,113,431
- Issue date Sep 26, 2006
- Spansion LLC
- Darlene Hamilton
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for pulse erase in dual bit memory devices
- Patent number 7,092,297
- Issue date Aug 15, 2006
- Advanced Micro Devices, Inc.
- Satoshi Torii
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for programming dual bit memory devices to reduce complement...
- Patent number 7,079,423
- Issue date Jul 18, 2006
- Advanced Micro Devices, Inc.
- Satoshi Torii
- G11 - INFORMATION STORAGE
Information Patent Grant
Recessed channel with separated ONO memory device
- Patent number 7,067,377
- Issue date Jun 27, 2006
- FASL LLC
- Jaeyong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device with barrier layer
- Patent number 7,053,445
- Issue date May 30, 2006
- Spansion LLC
- Youseok Suh
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND ARCHITECTURE FOR FAST FLASH MEMORY PROGRAMMING
- Publication number 20090175088
- Publication date Jul 9, 2009
- Satoshi TORII
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD FOR A MEMORY ARRAY WITH SHALLOW TRENCH ISOLATI...
- Publication number 20090047762
- Publication date Feb 19, 2009
- Satoshi TORII
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory Device with Barrier Layer
- Publication number 20080191269
- Publication date Aug 14, 2008
- SPANSION LLC
- Youseok Suh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
P-CHANNEL NAND IN ISOLATED N-WELL
- Publication number 20080135918
- Publication date Jun 12, 2008
- SPANSION LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SONOS memory with inversion bit-lines
- Publication number 20070058442
- Publication date Mar 15, 2007
- Hidehiko Shiraiwa
- G11 - INFORMATION STORAGE
Information Patent Application
Formation method of an array source line in NAND flash memory
- Publication number 20060240617
- Publication date Oct 26, 2006
- Spansion LLC
- Satoshi Torii
- H01 - BASIC ELECTRIC ELEMENTS

Satoshi Torii

Person

Patents Grantslast 30 patents

Apparatus and method for a memory array with shallow trench isolati...

Memory device with barrier layer

Method and architecture for fast flash memory programming

Multiple dual bit memory integrated circuit system

P-channel NAND in isolated N-well

Method and architecture for fast flash memory programming

SONOS memory with inversion bit-lines

Apparatus and method for a memory array with shallow trench isolati...

Methods for fabricating flash memory devices

Recessed channel with separated ONO memory device

Formation method of an array source line in NAND flash memory

Aluminum oxide as liner or cover layer to spacers in memory device

System and method for erasing a memory cell

SONOS memory with inversion bit-lines

Quad bit using hot-hole erase for CBD control

Method for pulse erase in dual bit memory devices

Method for programming dual bit memory devices to reduce complement...

Recessed channel with separated ONO memory device

Memory device with barrier layer

Patents Applicationslast 30 patents

METHOD AND ARCHITECTURE FOR FAST FLASH MEMORY PROGRAMMING

APPARATUS AND METHOD FOR A MEMORY ARRAY WITH SHALLOW TRENCH ISOLATI...

Memory Device with Barrier Layer

P-CHANNEL NAND IN ISOLATED N-WELL

SONOS memory with inversion bit-lines

Formation method of an array source line in NAND flash memory