Satwant Singh

Person

Macungie, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Fast boot systems and methods for programmable logic devices
- Patent number 11,847,471
- Issue date Dec 19, 2023
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast boot systems and methods for programmable logic devices
- Patent number 11,132,207
- Issue date Sep 28, 2021
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital signal processing block architecture for programmable logic...
- Patent number 8,463,832
- Issue date Jun 11, 2013
- Lattice Semiconductor Corporation
- Asher Hazanchuk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Soft error upset hardened integrated circuit systems and methods
- Patent number 7,868,646
- Issue date Jan 11, 2011
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Redundant configuration memory systems and methods
- Patent number 7,746,107
- Issue date Jun 29, 2010
- Lattice Semiconductor Corporation
- Satwant Singh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Soft error upset hardened integrated circuit systems and methods
- Patent number 7,741,865
- Issue date Jun 22, 2010
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power management for integrated circuits such as programmable logic...
- Patent number 7,724,029
- Issue date May 25, 2010
- Lattice Semiconductor Corporation
- Satwant Singh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Redundant configuration memory systems and methods
- Patent number 7,598,765
- Issue date Oct 6, 2009
- Lattice Semiconductor Corporation
- Satwant Singh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with enhanced logic block architecture
- Patent number 7,573,291
- Issue date Aug 11, 2009
- Lattice Semiconductor Corporation
- Om Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power management systems and methods for programmable logic devices
- Patent number 7,560,953
- Issue date Jul 14, 2009
- Lattice Semiconductor Corporation
- Satwant Singh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-verification of configuration memory in programmable logic dev...
- Patent number 7,401,280
- Issue date Jul 15, 2008
- Lattice Semiconductor Corporation
- Satwant Singh
- G11 - INFORMATION STORAGE
Information Patent Grant
In-system programming of a non-compliant device using multiple inte...
- Patent number 7,397,274
- Issue date Jul 8, 2008
- Lattice Semiconductor Corporation
- Howard Tang
- G01 - MEASURING TESTING
Information Patent Grant
Method and systems to align outputs signals of an analog-to-digital...
- Patent number 7,348,914
- Issue date Mar 25, 2008
- Lattice Semiconductor Corporation
- Asher Hazanchuk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with enhanced logic block architecture
- Patent number 7,295,035
- Issue date Nov 13, 2007
- Lattice Semiconductor Corporation
- Om Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
In-system programming of non-JTAG device using SPI and JTAG interfa...
- Patent number 7,265,578
- Issue date Sep 4, 2007
- Lattice Semiconductor Corporation
- Howard Tang
- G01 - MEASURING TESTING
Information Patent Grant
Self-verification of configuration memory in programmable logic dev...
- Patent number 7,257,750
- Issue date Aug 14, 2007
- Lattice Semiconductor Corporation
- Satwant Singh
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuring FPGAs and the like using one or more serial memory devices
- Patent number 7,095,247
- Issue date Aug 22, 2006
- Lattice Semiconductor Corporation
- Howard Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configuring FPGAs and the like using one or more serial memory devices
- Patent number 7,088,132
- Issue date Aug 8, 2006
- Lattice Semiconductor Corporation
- Howard Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output impedance measurement techniques
- Patent number 7,057,397
- Issue date Jun 6, 2006
- Lattice Semiconductor Corporation
- Allan T. Davidson
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay-matched ASIC conversion of a programmable logic device
- Patent number 7,038,490
- Issue date May 2, 2006
- Lattice Semiconductor Corporation
- Satwant Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FIFO memory with programmable data port widths
- Patent number 6,986,004
- Issue date Jan 10, 2006
- Lattice Semiconductor Corporation
- Chan-Chi Jason Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Macrocells supporting a carry cascade
- Patent number 6,915,323
- Issue date Jul 5, 2005
- Lattice Semiconductor Corporation
- Jason Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with enhanced wide input product term cas...
- Patent number 6,903,573
- Issue date Jun 7, 2005
- Lattice Semiconductor Corporation
- Jason Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scalable device architecture for high-speed interfaces
- Patent number 6,903,575
- Issue date Jun 7, 2005
- Lattice Semiconductor Corporation
- Allan T. Davidson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable and fixed logic circuitry for high-speed interfaces
- Patent number 6,894,530
- Issue date May 17, 2005
- Lattice Semiconductor Corporation
- Allan T. Davidson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic cross point switch with shadow memory architecture
- Patent number 6,861,870
- Issue date Mar 1, 2005
- Lattice Semiconductor Corporation
- Jason Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Device and method with generic logic blocks
- Patent number 6,765,408
- Issue date Jul 20, 2004
- Lattice Semiconductor Corporation
- Jason Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Global signal distribution with reduced routing tracks in an FPGA
- Patent number 6,064,225
- Issue date May 16, 2000
- Lucent Technologies Inc.
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with logic cells having a flexible input...
- Patent number 6,049,224
- Issue date Apr 11, 2000
- Lucent Technologies Inc.
- Barry K. Britton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA having predictable open-drain drive mode
- Patent number 6,028,447
- Issue date Feb 22, 2000
- Lucent Technologies Inc.
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CONFIGURABLE CLOCK ENABLE AND RESET SIGNAL FOR PROGRAMMABLE LOGIC D...
- Publication number 20240184968
- Publication date Jun 6, 2024
- Lattice Semiconductor Corporation
- Satwant Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE LOOK-UP TABLE SYSTEMS AND METHODS
- Publication number 20230216503
- Publication date Jul 6, 2023
- Lattice Semiconductor Corporation
- Satwant Singh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REMOTE PROGRAMMING SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20220229411
- Publication date Jul 21, 2022
- Lattice Semiconductor Corporation
- Rahulkumar Koche
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20220012064
- Publication date Jan 13, 2022
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20190205144
- Publication date Jul 4, 2019
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUNDANT CONFIGURATION MEMORY SYSTEMS AND METHODS
- Publication number 20080204073
- Publication date Aug 28, 2008
- Satwant Singh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Device and method with generic logic blocks
- Publication number 20040000928
- Publication date Jan 1, 2004
- Lattice Semiconductor Corporation
- Jason Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY

Satwant Singh

Person

Patents Grantslast 30 patents

Fast boot systems and methods for programmable logic devices

Fast boot systems and methods for programmable logic devices

Digital signal processing block architecture for programmable logic...

Soft error upset hardened integrated circuit systems and methods

Redundant configuration memory systems and methods

Soft error upset hardened integrated circuit systems and methods

Power management for integrated circuits such as programmable logic...

Redundant configuration memory systems and methods

Programmable logic device with enhanced logic block architecture

Power management systems and methods for programmable logic devices

Self-verification of configuration memory in programmable logic dev...

In-system programming of a non-compliant device using multiple inte...

Method and systems to align outputs signals of an analog-to-digital...

Programmable logic device with enhanced logic block architecture

In-system programming of non-JTAG device using SPI and JTAG interfa...

Self-verification of configuration memory in programmable logic dev...

Configuring FPGAs and the like using one or more serial memory devices

Configuring FPGAs and the like using one or more serial memory devices

Output impedance measurement techniques

Delay-matched ASIC conversion of a programmable logic device

FIFO memory with programmable data port widths

Macrocells supporting a carry cascade

Programmable logic device with enhanced wide input product term cas...

Scalable device architecture for high-speed interfaces

Programmable and fixed logic circuitry for high-speed interfaces

Dynamic cross point switch with shadow memory architecture

Device and method with generic logic blocks

Global signal distribution with reduced routing tracks in an FPGA

Programmable logic device with logic cells having a flexible input...

FPGA having predictable open-drain drive mode

Patents Applicationslast 30 patents

CONFIGURABLE CLOCK ENABLE AND RESET SIGNAL FOR PROGRAMMABLE LOGIC D...

PROGRAMMABLE LOOK-UP TABLE SYSTEMS AND METHODS

REMOTE PROGRAMMING SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES

FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES

FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES

REDUNDANT CONFIGURATION MEMORY SYSTEMS AND METHODS

Device and method with generic logic blocks