Satyendra S. Chauhan

Person

Sugarland, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Stress relief for flip-chip packaged devices
- Patent number 11,930,590
- Issue date Mar 12, 2024
- Texas Instruments Incorporated
- Tianyi Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with solder standoff
- Patent number 11,908,780
- Issue date Feb 20, 2024
- Texas Instruments Incorporated
- Jonathan Almeria Noquil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive plate stress reduction feature
- Patent number 11,658,130
- Issue date May 23, 2023
- Texas Instruments Incorporated
- Tianyi Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hall-effect sensor package with added current path
- Patent number 11,557,722
- Issue date Jan 17, 2023
- Texas Instruments Incorporated
- Ming Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip module including stacked power devices with metal clip
- Patent number 11,495,580
- Issue date Nov 8, 2022
- Texas Instruments Incorporated
- Marie Denison
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with solder standoff
- Patent number 11,177,197
- Issue date Nov 16, 2021
- Texas Instruments Incorporated
- Jonathan Almeria Noquil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hall-effect sensor package with added current path
- Patent number 10,892,405
- Issue date Jan 12, 2021
- Texas Instruments Incorporated
- Ming Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip module including stacked power devices with metal clip
- Patent number 10,128,219
- Issue date Nov 13, 2018
- Texas Instruments Incorporated
- Marie Denison
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC device having low resistance TSV comprising ground connection
- Patent number 8,436,475
- Issue date May 7, 2013
- Texas Instruments Incorporated
- Rajiv Dunne
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC device having low resistance TSV comprising ground connection
- Patent number 8,431,481
- Issue date Apr 30, 2013
- Texas Instruments Incorporated
- Rajiv Dunne
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thru silicon enabled die stacking scheme
- Patent number 8,193,093
- Issue date Jun 5, 2012
- Texas Instruments Incorporated
- Satyendra Singh Chauhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC device having low resistance TSV comprising ground connection
- Patent number 8,178,976
- Issue date May 15, 2012
- Texas Instruments Incorporated
- Rajiv Dunne
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged electronic devices with face-up die having TSV connection...
- Patent number 8,154,134
- Issue date Apr 10, 2012
- Texas Instruments Incorporated
- Thomas D. Bonifield
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC having voltage regulated integrated Faraday shield
- Patent number 8,053,873
- Issue date Nov 8, 2011
- Texas Instruments Incorporated
- Satyendra S Chauhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for post-circuitization assembly
- Patent number 8,039,309
- Issue date Oct 18, 2011
- Texas Instruments Incorporated
- Masood Murtuza
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual carrier for joining IC die or wafers to TSV wafers
- Patent number 8,017,439
- Issue date Sep 13, 2011
- Texas Instruments Incorporated
- Yoshimi Takahashi
- C09 - DYES PAINTS POLISHES NATURAL RESINS ADHESIVES MISCELLANEOUS COMPOSITION...
Information Patent Grant
Thru silicon enabled die stacking scheme
- Patent number 7,973,416
- Issue date Jul 5, 2011
- Texas Instruments Incorporated
- Satyendra Singh Chauhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonding IC die to TSV wafers
- Patent number 7,915,080
- Issue date Mar 29, 2011
- Texas Instruments Incorporated
- Yoshimi Takahashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi layer low cost cavity substrate fabrication for PoP packages
- Patent number 7,883,936
- Issue date Feb 8, 2011
- Texas Instruments Incorporated
- Prema Palaniappan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder cap application process on copper bump using solder powder film
- Patent number 7,790,597
- Issue date Sep 7, 2010
- Texas Instruments Incorporated
- Satyendra S. Chauhan
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multi layer low cost cavity substrate fabrication for pop packages
- Patent number 7,635,914
- Issue date Dec 22, 2009
- Texas Instruments Incorporated
- Prema Palaniappan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fine pitch low cost flip chip substrate
- Patent number 7,323,405
- Issue date Jan 29, 2008
- Texas Instruments Incorporated
- Satyendra S. Chauhan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Fine pitch low-cost flip chip substrate
- Patent number 7,057,284
- Issue date Jun 6, 2006
- Texas Instruments Incorporated
- Satyendra S. Chauhan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Built-up bump pad structure and method for same
- Patent number 6,888,255
- Issue date May 3, 2005
- Texas Instruments Incorporated
- Masood Murtuza
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Using a supporting structure to control collapse of a die towards a...
- Patent number 6,849,944
- Issue date Feb 1, 2005
- Texas Instruments Incorporated
- Masood Murtuza
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
STRESS RELIEF FOR FLIP-CHIP PACKAGED DEVICES
- Publication number 20240224415
- Publication date Jul 4, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Tianyi Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESS RELIEF FOR FLIP-CHIP PACKAGED DEVICES
- Publication number 20220210911
- Publication date Jun 30, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Tianyi Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE PLATE STRESS REDUCTION FEATURE
- Publication number 20220208692
- Publication date Jun 30, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Tianyi Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH SOLDER STANDOFF
- Publication number 20220115308
- Publication date Apr 14, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Jonathan Almeria Noquil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HALL-EFFECT SENSOR PACKAGE WITH ADDED CURRENT PATH
- Publication number 20210159403
- Publication date May 27, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Ming Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH SOLDER STANDOFF
- Publication number 20210090980
- Publication date Mar 25, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Jonathan Almeria Noquil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HALL-EFFECT SENSOR PACKAGE WITH ADDED CURRENT PATH
- Publication number 20200357987
- Publication date Nov 12, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Ming Li
- G01 - MEASURING TESTING
Information Patent Application
MULTI-CHIP MODULE INCLUDING STACKED POWER DEVICES WITH METAL CLIP
- Publication number 20190088628
- Publication date Mar 21, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Marie Denison
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP MODULE INCLUDING STACKED POWER DEVICES WITH METAL CLIP
- Publication number 20130285260
- Publication date Oct 31, 2013
- TEXAS INSTRUMENTS INCORPORATED
- MARIE DENISON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC Device Having Low Resistance TSV Comprising Ground Connection
- Publication number 20120202321
- Publication date Aug 9, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Rajiv Dunne
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC Device Having Low Resistance TSV Comprising Ground Connection
- Publication number 20120193814
- Publication date Aug 2, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Rajiv Dunne
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THRU SILICON ENABLED DIE STACKING SCHEME
- Publication number 20110250720
- Publication date Oct 13, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Satyendra Singh CHAUHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL CARRIER FOR JOINING IC DIE OR WAFERS TO TSV WAFERS
- Publication number 20110183464
- Publication date Jul 28, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Yoshimi Takahashi
- C09 - DYES PAINTS POLISHES NATURAL RESINS ADHESIVES MISCELLANEOUS COMPOSITION...
Information Patent Application
THRU SILICON ENABLED DIE STACKING SCHEME
- Publication number 20100320575
- Publication date Dec 23, 2010
- Satyendra Singh CHAUHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THRU SILICON ENABLED DIE STACKING SCHEME
- Publication number 20100200961
- Publication date Aug 12, 2010
- Satyendra Singh CHAUHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BONDING IC DIE TO TSV WAFERS
- Publication number 20100159643
- Publication date Jun 24, 2010
- TEXAS INSTRUMENTS INCORPORATED
- YOSHIMI TAKAHASHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi Layer Low Cost Cavity Substrate Fabrication for POP Packages
- Publication number 20100062567
- Publication date Mar 11, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Prema Palaniappan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC HAVING VOLTAGE REGULATED INTEGRATED FARADAY SHIELD
- Publication number 20090302438
- Publication date Dec 10, 2009
- TEXAS INSTRUMENTS INCORPORATED
- SATYENDRA SINGH CHAUHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED ELECTRONIC DEVICES WITH FACE-UP DIE HAVING TSV CONNECTION...
- Publication number 20090278245
- Publication date Nov 12, 2009
- Texas Instruments Inc.
- THOMAS D. BONIFIELD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC DEVICE HAVING LOW RESISTANCE TSV COMPRISING GROUND CONNECTION
- Publication number 20090278244
- Publication date Nov 12, 2009
- Texas Instruments Inc.
- RAJIV DUNNE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOLDER CAP APPLICATION PROCESS ON COPPER BUMP USING SOLDER POWDER FILM
- Publication number 20090014898
- Publication date Jan 15, 2009
- Satyendra S. Chauhan
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
Multi layer low cost cavity substrate fabrication for pop packages
- Publication number 20080283992
- Publication date Nov 20, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Prema Palaniappan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEMS AND METHODS FOR POST-CIRCUITIZATION ASSEMBLY
- Publication number 20080280394
- Publication date Nov 13, 2008
- Masood Murtuza
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINE PITCH LOW COST FLIP CHIP SUBSTRATE
- Publication number 20060180919
- Publication date Aug 17, 2006
- Satyendra S. Chauhan
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Fine pitch low-cost flip chip substrate
- Publication number 20060033210
- Publication date Feb 16, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Satyendra S. Chauhan
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Built-up bump pad structure and method for same
- Publication number 20040238953
- Publication date Dec 2, 2004
- Masood Murtuza
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
USING A SUPPORTING STRUCTURE TO CONTROL COLLAPSE OF A DIE TOWARDS A...
- Publication number 20040238956
- Publication date Dec 2, 2004
- Masood Murtuza
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Satyendra S. Chauhan

Person

Patents Grantslast 30 patents

Stress relief for flip-chip packaged devices

Semiconductor package with solder standoff

Conductive plate stress reduction feature

Hall-effect sensor package with added current path

Multi-chip module including stacked power devices with metal clip

Semiconductor package with solder standoff

Hall-effect sensor package with added current path

Multi-chip module including stacked power devices with metal clip

IC device having low resistance TSV comprising ground connection

IC device having low resistance TSV comprising ground connection

Thru silicon enabled die stacking scheme

IC device having low resistance TSV comprising ground connection

Packaged electronic devices with face-up die having TSV connection...

IC having voltage regulated integrated Faraday shield

Systems and methods for post-circuitization assembly

Dual carrier for joining IC die or wafers to TSV wafers

Thru silicon enabled die stacking scheme

Bonding IC die to TSV wafers

Multi layer low cost cavity substrate fabrication for PoP packages

Solder cap application process on copper bump using solder powder film

Multi layer low cost cavity substrate fabrication for pop packages

Fine pitch low cost flip chip substrate

Fine pitch low-cost flip chip substrate

Built-up bump pad structure and method for same

Using a supporting structure to control collapse of a die towards a...

Patents Applicationslast 30 patents

STRESS RELIEF FOR FLIP-CHIP PACKAGED DEVICES

STRESS RELIEF FOR FLIP-CHIP PACKAGED DEVICES

CONDUCTIVE PLATE STRESS REDUCTION FEATURE

SEMICONDUCTOR PACKAGE WITH SOLDER STANDOFF

HALL-EFFECT SENSOR PACKAGE WITH ADDED CURRENT PATH

SEMICONDUCTOR PACKAGE WITH SOLDER STANDOFF

HALL-EFFECT SENSOR PACKAGE WITH ADDED CURRENT PATH

MULTI-CHIP MODULE INCLUDING STACKED POWER DEVICES WITH METAL CLIP

MULTI-CHIP MODULE INCLUDING STACKED POWER DEVICES WITH METAL CLIP

IC Device Having Low Resistance TSV Comprising Ground Connection

IC Device Having Low Resistance TSV Comprising Ground Connection

THRU SILICON ENABLED DIE STACKING SCHEME

DUAL CARRIER FOR JOINING IC DIE OR WAFERS TO TSV WAFERS

THRU SILICON ENABLED DIE STACKING SCHEME

THRU SILICON ENABLED DIE STACKING SCHEME

BONDING IC DIE TO TSV WAFERS

Multi Layer Low Cost Cavity Substrate Fabrication for POP Packages

IC HAVING VOLTAGE REGULATED INTEGRATED FARADAY SHIELD

PACKAGED ELECTRONIC DEVICES WITH FACE-UP DIE HAVING TSV CONNECTION...

IC DEVICE HAVING LOW RESISTANCE TSV COMPRISING GROUND CONNECTION

SOLDER CAP APPLICATION PROCESS ON COPPER BUMP USING SOLDER POWDER FILM

Multi layer low cost cavity substrate fabrication for pop packages

SYSTEMS AND METHODS FOR POST-CIRCUITIZATION ASSEMBLY

FINE PITCH LOW COST FLIP CHIP SUBSTRATE

Fine pitch low-cost flip chip substrate

Built-up bump pad structure and method for same

USING A SUPPORTING STRUCTURE TO CONTROL COLLAPSE OF A DIE TOWARDS A...