Saurabh Mathur

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Saratoga, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Data processing array interface having interface tiles with multipl...
- Patent number 12,164,451
- Issue date Dec 10, 2024
- Xilinx, Inc.
- David Patrick Clarke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple partitions in a data processing array
- Patent number 11,848,670
- Issue date Dec 19, 2023
- Xilinx, Inc.
- Juan J. Noguera Serra
- G11 - INFORMATION STORAGE
Information Patent Grant
Activity-aware clock gating for switches
- Patent number 11,223,351
- Issue date Jan 11, 2022
- Xilinx, Inc.
- Amarnath Kasibhatla
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTIPLE PARTITIONS IN A DATA PROCESSING ARRAY
- Publication number 20240088900
- Publication date Mar 14, 2024
- Xilinx, Inc.
- Juan J. Noguera Serra
- G11 - INFORMATION STORAGE
Information Patent Application
DATA PROCESSING ARRAY INTERFACE HAVING INTERFACE TILES WITH MULTIPL...
- Publication number 20230376437
- Publication date Nov 23, 2023
- Xilinx, Inc.
- David Patrick Clarke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE PARTITIONS IN A DATA PROCESSING ARRAY
- Publication number 20230336179
- Publication date Oct 19, 2023
- Xilinx, Inc.
- Juan J. Noguera Serra
- G11 - INFORMATION STORAGE