Saurabh MORARKA

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
FinFET varactor quality factor improvement
- Patent number 11,961,836
- Issue date Apr 16, 2024
- Intel Corporation
- Hyung-Jin Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures including varactors
- Patent number 11,869,987
- Issue date Jan 9, 2024
- Intel Corporation
- Ayan Kar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming dislocation enhanced strain in NMOS and PMOS str...
- Patent number 11,610,995
- Issue date Mar 21, 2023
- Daedalus Prime LLC
- Michael Jackson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field-effect transistors with asymmetric gate stacks
- Patent number 11,515,424
- Issue date Nov 29, 2022
- Intel Corporation
- Said Rami
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming dislocation enhanced strain in NMOS and PMOS str...
- Patent number 11,482,618
- Issue date Oct 25, 2022
- Daedalus Prime LLC
- Michael Jackson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures including varactors
- Patent number 11,417,781
- Issue date Aug 16, 2022
- Intel Corporation
- Ayan Kar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming dislocation enhanced strain in NMOS and PMOS str...
- Patent number 11,411,110
- Issue date Aug 9, 2022
- Intel Corporation
- Michael Jackson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming dislocation enhanced strain in NMOS structures
- Patent number 11,107,920
- Issue date Aug 31, 2021
- Intel Corporation
- Michael Jackson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming dislocation enhanced strain in NMOS structures
- Patent number 10,396,201
- Issue date Aug 27, 2019
- Intel Corporation
- Michael Jackson
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
VARACTOR DEVICE WITH BACKSIDE ELECTRICAL CONTACT
- Publication number 20230420578
- Publication date Dec 28, 2023
- Intel Corporation
- Ayan Kar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PARTIAL GATE CUT STRUCTURES IN AN INTEGRATED CIRCUIT
- Publication number 20230299135
- Publication date Sep 21, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE CONTACTS WRAPPED AROUND EPITAXIAL SOURCE OR DRAIN REGIONS
- Publication number 20230275124
- Publication date Aug 31, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STR...
- Publication number 20230197848
- Publication date Jun 22, 2023
- Daedalus Prime LLC
- Michael Jackson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STR...
- Publication number 20230006063
- Publication date Jan 5, 2023
- Daedalus Prime LLC
- Michael Jackson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE VIA BAR SELF-ALIGNED TO GATE END
- Publication number 20220399445
- Publication date Dec 15, 2022
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING CUT METAL GATES WITH DIELECTRI...
- Publication number 20220399373
- Publication date Dec 15, 2022
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES INCLUDING VARACTORS
- Publication number 20220344519
- Publication date Oct 27, 2022
- Intel Corporation
- Ayan KAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STR...
- Publication number 20220238714
- Publication date Jul 28, 2022
- Intel Corporation
- Michael JACKSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STR...
- Publication number 20220059699
- Publication date Feb 24, 2022
- Intel Corporation
- Michael JACKSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES INCLUDING VARACTORS
- Publication number 20210305436
- Publication date Sep 30, 2021
- Intel Corporation
- Ayan KAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD-EFFECT TRANSISTORS WITH ASYMMETRIC GATE STACKS
- Publication number 20200259018
- Publication date Aug 13, 2020
- Intel Corporation
- Said Rami
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINFET VARACTOR QUALITY FACTOR IMPROVEMENT
- Publication number 20200105747
- Publication date Apr 2, 2020
- Intel Corporation
- Hyung-Jin LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS STRUCTURES
- Publication number 20190334034
- Publication date Oct 31, 2019
- Intel Corporation
- Michael JACKSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RESISTANCE REDUCTION UNDER TRANSISTOR SPACERS
- Publication number 20180240874
- Publication date Aug 23, 2018
- Intel Corporation
- CORY E. WEBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS STRUCTURES
- Publication number 20160204256
- Publication date Jul 14, 2016
- Michael Jackson
- H01 - BASIC ELECTRIC ELEMENTS

Saurabh MORARKA

Person

Patents Grantslast 30 patents

FinFET varactor quality factor improvement

Gate-all-around integrated circuit structures including varactors

Methods of forming dislocation enhanced strain in NMOS and PMOS str...

Field-effect transistors with asymmetric gate stacks

Methods of forming dislocation enhanced strain in NMOS and PMOS str...

Gate-all-around integrated circuit structures including varactors

Methods of forming dislocation enhanced strain in NMOS and PMOS str...

Methods of forming dislocation enhanced strain in NMOS structures

Methods of forming dislocation enhanced strain in NMOS structures

Patents Applicationslast 30 patents

VARACTOR DEVICE WITH BACKSIDE ELECTRICAL CONTACT

PARTIAL GATE CUT STRUCTURES IN AN INTEGRATED CIRCUIT

CONDUCTIVE CONTACTS WRAPPED AROUND EPITAXIAL SOURCE OR DRAIN REGIONS

METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STR...

METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STR...

CONDUCTIVE VIA BAR SELF-ALIGNED TO GATE END

INTEGRATED CIRCUIT STRUCTURES HAVING CUT METAL GATES WITH DIELECTRI...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES INCLUDING VARACTORS

METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STR...

METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STR...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES INCLUDING VARACTORS

FIELD-EFFECT TRANSISTORS WITH ASYMMETRIC GATE STACKS

FINFET VARACTOR QUALITY FACTOR IMPROVEMENT

METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS STRUCTURES

RESISTANCE REDUCTION UNDER TRANSISTOR SPACERS

METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS STRUCTURES