SAURABH SHARMA

Person

El Dorado Hills, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Stochastic optimization of surface cacheability in parallel process...
- Patent number 12,117,939
- Issue date Oct 15, 2024
- Advanced Micro Devices, Inc.
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dead surface invalidation
- Patent number 12,033,239
- Issue date Jul 9, 2024
- Advanced Micro Devices, Inc.
- Priyadarshi Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tile sequencing mechanism
- Patent number 11,900,539
- Issue date Feb 13, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Position-based rendering apparatus and method for multi-die/GPU gra...
- Patent number 11,710,269
- Issue date Jul 25, 2023
- Intel Corporation
- Travis Schluessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compressing texture data on a per-channel basis
- Patent number 11,694,367
- Issue date Jul 4, 2023
- Advanced Micro Devices, Inc.
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically enabling tiling in 3D workloads
- Patent number 11,640,693
- Issue date May 2, 2023
- Intel Corporation
- Justin DeCell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical depth buffer back annotation
- Patent number 11,615,584
- Issue date Mar 28, 2023
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous execution mechanism
- Patent number 11,494,867
- Issue date Nov 8, 2022
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Position-based rendering apparatus and method for multi-die/GPU gra...
- Patent number 11,403,805
- Issue date Aug 2, 2022
- Intel Corporation
- Travis Schluessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compressing texture data on a per-channel basis
- Patent number 11,308,648
- Issue date Apr 19, 2022
- Advanced Micro Devices, Inc.
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequent data value compression for graphics processing units
- Patent number 11,263,720
- Issue date Mar 1, 2022
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tile sequencing mechanism
- Patent number 11,250,627
- Issue date Feb 15, 2022
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low granularity coarse depth test efficiency enhancement
- Patent number 11,250,539
- Issue date Feb 15, 2022
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for scheduling thread order to improve cache e...
- Patent number 11,204,801
- Issue date Dec 21, 2021
- Intel Corporation
- Justin DeCell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically enabling tiling in 3D workloads
- Patent number 11,176,736
- Issue date Nov 16, 2021
- Intel Corporation
- Justin DeCell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical depth buffer back annotation
- Patent number 11,080,925
- Issue date Aug 3, 2021
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for a prescriptive engine
- Patent number 11,055,643
- Issue date Jul 6, 2021
- Samsung Electronics Co., Ltd.
- Matthew Fritz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Position-based rendering apparatus and method for multi-die/GPU gra...
- Patent number 10,997,771
- Issue date May 4, 2021
- Intel Corporation
- Travis Schluessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically enabling tiling in 3D workloads
- Patent number 10,916,052
- Issue date Feb 9, 2021
- Intel Corporation
- Justin DeCell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous execution mechanism
- Patent number 10,861,126
- Issue date Dec 8, 2020
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single input multiple data processing mechanism
- Patent number 10,769,751
- Issue date Sep 8, 2020
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low granularity coarse depth test efficiency enhancement
- Patent number 10,748,242
- Issue date Aug 18, 2020
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequent data value compression for graphics processing units
- Patent number 10,748,238
- Issue date Aug 18, 2020
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for adaptive pixel hashing for graphics proces...
- Patent number 10,546,362
- Issue date Jan 28, 2020
- Intel Corporation
- Kalyan K. Bhiravabhatla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical depth buffer back annotaton
- Patent number 10,424,107
- Issue date Sep 24, 2019
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single input multiple data processing mechanism
- Patent number 10,417,730
- Issue date Sep 17, 2019
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequent data value compression for graphics processing units
- Patent number 10,262,388
- Issue date Apr 16, 2019
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for performing partial cache line writes without...
- Patent number 10,146,691
- Issue date Dec 4, 2018
- Intel Corporation
- Hashem Hashemi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Specialized code paths in GPU processing
- Patent number 10,140,678
- Issue date Nov 27, 2018
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low granularity coarse depth test efficiency enhancement
- Patent number 10,102,609
- Issue date Oct 16, 2018
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTERMEDIATE CACHE MANAGEMENT FOR NON-UNIFORM MEMORY ARCHITECTURE
- Publication number 20240411706
- Publication date Dec 12, 2024
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAVERSAL RECURSION FOR ACCELERATION STRUCTURE TRAVERSAL
- Publication number 20240370965
- Publication date Nov 7, 2024
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSING TEXTURE DATA ON A PER-CHANNEL BASIS
- Publication number 20240273767
- Publication date Aug 15, 2024
- ADVANCED MICRO DEVICES, INC.
- Saurabh SHARMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TILE SEQUENCING MECHANISM
- Publication number 20240185527
- Publication date Jun 6, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEAD SURFACE INVALIDATION
- Publication number 20230206384
- Publication date Jun 29, 2023
- ADVANCED MICRO DEVICES, INC.
- Priyadarshi Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE BLOCKING FOR DISPATCHES
- Publication number 20230205698
- Publication date Jun 29, 2023
- ADVANCED MICRO DEVICES, INC.
- Saurabh SHARMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE DISPATCH WALK FOR SUCCESSIVE CACHE ACCESSES
- Publication number 20230195626
- Publication date Jun 22, 2023
- ADVANCED MICRO DEVICES, INC.
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STOCHASTIC OPTIMIZATION OF SURFACE CACHEABILITY IN PARALLEL PROCESS...
- Publication number 20230195639
- Publication date Jun 22, 2023
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE DISPATCH WALK
- Publication number 20230195509
- Publication date Jun 22, 2023
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSING TEXTURE DATA ON A PER-CHANNEL BASIS
- Publication number 20230048839
- Publication date Feb 16, 2023
- ADVANCED MICRO DEVICES, INC.
- Saurabh SHARMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POSITION-BASED RENDERING APPARATUS AND METHOD FOR MULTI-DIE/GPU GRA...
- Publication number 20220366630
- Publication date Nov 17, 2022
- Intel Corporation
- TRAVIS SCHLUESSLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TILE SEQUENCING MECHANISM
- Publication number 20220262070
- Publication date Aug 18, 2022
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY ENABLING TILING IN 3D WORKLOADS
- Publication number 20220148261
- Publication date May 12, 2022
- Intel Corporation
- Justin DeCell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSING TEXTURE DATA ON A PER-CHANNEL BASIS
- Publication number 20220092826
- Publication date Mar 24, 2022
- ADVANCED MICRO DEVICES, INC.
- Saurabh SHARMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL DEPTH BUFFER BACK ANNOTATION
- Publication number 20220051473
- Publication date Feb 17, 2022
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TILE SEQUENCING MECHANISM
- Publication number 20210407194
- Publication date Dec 30, 2021
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPACTION OF DIVERGED LANES FOR EFFICIENT USE OF ALUS
- Publication number 20210349717
- Publication date Nov 11, 2021
- Intel Corporation
- Chandra Gurram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POSITION-BASED RENDERING APPARATUS AND METHOD FOR MULTI-DIE/GPU GRA...
- Publication number 20210272349
- Publication date Sep 2, 2021
- Intel Corporation
- TRAVIS SCHLUESSLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS EXECUTION MECHANISM
- Publication number 20210256653
- Publication date Aug 19, 2021
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY ENABLING TILING IN 3D WORKLOADS
- Publication number 20210217235
- Publication date Jul 15, 2021
- Intel Corporation
- Justin DeCell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SCHEDULING THREAD ORDER TO IMPROVE CACHE E...
- Publication number 20210149716
- Publication date May 20, 2021
- Intel Corporation
- Justin DeCell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Frequent Data Value Compression for Graphics Processing Units
- Publication number 20210035257
- Publication date Feb 4, 2021
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW GRANULARITY COARSE DEPTH TEST EFFICIENCY ENHANCEMENT
- Publication number 20210035259
- Publication date Feb 4, 2021
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS EXECUTION MECHANISM
- Publication number 20200402196
- Publication date Dec 24, 2020
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY ENABLING TILING IN 3D WORKLOADS
- Publication number 20200342662
- Publication date Oct 29, 2020
- Intel Corporation
- Justin DeCell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL DEPTH BUFFER BACK ANNOTATON
- Publication number 20200098167
- Publication date Mar 26, 2020
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POSITION-BASED RENDERING APPARATUS AND METHOD FOR MULTI-DIE/GPU GRA...
- Publication number 20200074713
- Publication date Mar 5, 2020
- TRAVIS SCHLUESSLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE INPUT MULTIPLE DATA PROCESSING MECHANISM
- Publication number 20200043124
- Publication date Feb 6, 2020
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Frequent Data Value Compression for Graphics Processing Units
- Publication number 20190272613
- Publication date Sep 5, 2019
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Frequent Data Value Compression for Graphics Processing Units
- Publication number 20190251655
- Publication date Aug 15, 2019
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING

SAURABH SHARMA

Person

Patents Grantslast 30 patents

Stochastic optimization of surface cacheability in parallel process...

Dead surface invalidation

Tile sequencing mechanism

Position-based rendering apparatus and method for multi-die/GPU gra...

Compressing texture data on a per-channel basis

Dynamically enabling tiling in 3D workloads

Hierarchical depth buffer back annotation

Asynchronous execution mechanism

Position-based rendering apparatus and method for multi-die/GPU gra...

Compressing texture data on a per-channel basis

Frequent data value compression for graphics processing units

Tile sequencing mechanism

Low granularity coarse depth test efficiency enhancement

Method and apparatus for scheduling thread order to improve cache e...

Dynamically enabling tiling in 3D workloads

Hierarchical depth buffer back annotation

System and method for a prescriptive engine

Position-based rendering apparatus and method for multi-die/GPU gra...

Dynamically enabling tiling in 3D workloads

Asynchronous execution mechanism

Single input multiple data processing mechanism

Low granularity coarse depth test efficiency enhancement

Frequent data value compression for graphics processing units

Method and apparatus for adaptive pixel hashing for graphics proces...

Hierarchical depth buffer back annotaton

Single input multiple data processing mechanism

Frequent data value compression for graphics processing units

System and method for performing partial cache line writes without...

Specialized code paths in GPU processing

Low granularity coarse depth test efficiency enhancement

Patents Applicationslast 30 patents

INTERMEDIATE CACHE MANAGEMENT FOR NON-UNIFORM MEMORY ARCHITECTURE

TRAVERSAL RECURSION FOR ACCELERATION STRUCTURE TRAVERSAL

COMPRESSING TEXTURE DATA ON A PER-CHANNEL BASIS

TILE SEQUENCING MECHANISM

DEAD SURFACE INVALIDATION

CACHE BLOCKING FOR DISPATCHES

VARIABLE DISPATCH WALK FOR SUCCESSIVE CACHE ACCESSES

STOCHASTIC OPTIMIZATION OF SURFACE CACHEABILITY IN PARALLEL PROCESS...

VARIABLE DISPATCH WALK

COMPRESSING TEXTURE DATA ON A PER-CHANNEL BASIS

POSITION-BASED RENDERING APPARATUS AND METHOD FOR MULTI-DIE/GPU GRA...

TILE SEQUENCING MECHANISM

DYNAMICALLY ENABLING TILING IN 3D WORKLOADS

COMPRESSING TEXTURE DATA ON A PER-CHANNEL BASIS

HIERARCHICAL DEPTH BUFFER BACK ANNOTATION

TILE SEQUENCING MECHANISM

COMPACTION OF DIVERGED LANES FOR EFFICIENT USE OF ALUS

POSITION-BASED RENDERING APPARATUS AND METHOD FOR MULTI-DIE/GPU GRA...

ASYNCHRONOUS EXECUTION MECHANISM

DYNAMICALLY ENABLING TILING IN 3D WORKLOADS

METHOD AND APPARATUS FOR SCHEDULING THREAD ORDER TO IMPROVE CACHE E...

Frequent Data Value Compression for Graphics Processing Units

LOW GRANULARITY COARSE DEPTH TEST EFFICIENCY ENHANCEMENT

ASYNCHRONOUS EXECUTION MECHANISM

DYNAMICALLY ENABLING TILING IN 3D WORKLOADS

HIERARCHICAL DEPTH BUFFER BACK ANNOTATON

POSITION-BASED RENDERING APPARATUS AND METHOD FOR MULTI-DIE/GPU GRA...

SINGLE INPUT MULTIPLE DATA PROCESSING MECHANISM

Frequent Data Value Compression for Graphics Processing Units

Frequent Data Value Compression for Graphics Processing Units