Savithri Sundareswaran

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for provisioning decoupling capacitance in an integrated cir...
- Patent number 9,465,899
- Issue date Oct 11, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Savithri Sundareswaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low leakage CMOS cell with low voltage swing
- Patent number 9,264,040
- Issue date Feb 16, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Savithri Sundareswaran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Timing closure using transistor sizing in standard cells
- Patent number 9,177,096
- Issue date Nov 3, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Savithri Sundareswaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing margins for on-chip variations from sensitivity data
- Patent number 8,656,331
- Issue date Feb 18, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Savithri Sundareswaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit having a standard cell and method for forming
- Patent number 8,618,838
- Issue date Dec 31, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Savithri Sundareswaran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reducing leakage in standard cells
- Patent number 8,612,915
- Issue date Dec 17, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Savithri Sundareswaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast on-chip decoupling capacitance budgeting method and device for...
- Patent number 7,571,404
- Issue date Aug 4, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Min Zhao
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Timing Closure Using Transistor Sizing in Standard Cells
- Publication number 20150278425
- Publication date Oct 1, 2015
- Savithri Sundareswaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LEAKAGE CMOS CELL WITH LOW VOLTAGE SWING
- Publication number 20150180452
- Publication date Jun 25, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Savithri Sundareswaran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD FOR PROVISIONING DECOUPLING CAPACITANCE IN AN INTEGRATED CIR...
- Publication number 20140282340
- Publication date Sep 18, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Savithri Sundareswaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT HAVING A STANDARD CELL AND METHOD FOR FORMING
- Publication number 20130069691
- Publication date Mar 21, 2013
- Savithri Sundareswaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST ON-CHIP DECOUPLING CAPACITANCE BUDGETING METHOD AND DEVICE FOR...
- Publication number 20080134103
- Publication date Jun 5, 2008
- MIN ZHAO
- G06 - COMPUTING CALCULATING COUNTING

Savithri Sundareswaran

Person

Patents Grantslast 30 patents

Method for provisioning decoupling capacitance in an integrated cir...

Low leakage CMOS cell with low voltage swing

Timing closure using transistor sizing in standard cells

Timing margins for on-chip variations from sensitivity data

Integrated circuit having a standard cell and method for forming

Reducing leakage in standard cells

Fast on-chip decoupling capacitance budgeting method and device for...

Patents Applicationslast 30 patents

Timing Closure Using Transistor Sizing in Standard Cells

LOW LEAKAGE CMOS CELL WITH LOW VOLTAGE SWING

METHOD FOR PROVISIONING DECOUPLING CAPACITANCE IN AN INTEGRATED CIR...

INTEGRATED CIRCUIT HAVING A STANDARD CELL AND METHOD FOR FORMING

FAST ON-CHIP DECOUPLING CAPACITANCE BUDGETING METHOD AND DEVICE FOR...