SCOTT BELL

Person

SAN JOSE, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Split-gate semiconductor device with L-shaped gate
- Patent number 10,593,688
- Issue date Mar 17, 2020
- Cypress Semiconductor Corporation
- Scott A. Bell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Split-gate semiconductor device with L-shaped gate
- Patent number 10,020,316
- Issue date Jul 10, 2018
- Cypress Semiconductor Corporation
- Scott Bell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ion implantation-assisted etch-back process for improving spacer sh...
- Patent number 9,735,289
- Issue date Aug 15, 2017
- Cypress Semiconductor Corporation
- Gong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried hard mask for embedded semiconductor device patterning
- Patent number 9,673,206
- Issue date Jun 6, 2017
- Cypress Semiconductor Corporation
- Scott A. Bell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Split-gate semiconductor device with L-shaped gate
- Patent number 9,589,805
- Issue date Mar 7, 2017
- Cypress Semiconductor Corporation
- Scott Bell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Spacer formation with straight sidewall
- Patent number 9,466,496
- Issue date Oct 11, 2016
- Cypress Semiconductor Corporation
- Angela Tai Hui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrating transistors with different poly-silicon heights on the...
- Patent number 9,431,503
- Issue date Aug 30, 2016
- Cypress Semiconductor Corporation
- Chuan Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried hard mask for embedded semiconductor device patterning
- Patent number 9,318,498
- Issue date Apr 19, 2016
- Cypress Semiconductor Corporation
- Scott A. Bell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of gate sidewall structure
- Patent number 9,252,221
- Issue date Feb 2, 2016
- Cypress Semiconductor Corporation
- Rinji Sugino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming narrow structures in a semiconductor device
- Patent number 8,901,720
- Issue date Dec 2, 2014
- Advanced Micro Devices, Inc.
- Michael Brennan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with metal and semi-conducting gate
- Patent number 8,815,727
- Issue date Aug 26, 2014
- Advanced Micro Devices, Inc.
- Angela T. Hui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrating transistors with different poly-silicon heights on the...
- Patent number 8,652,907
- Issue date Feb 18, 2014
- Spansion LLC
- Chuan Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mask for forming integrated circuit
- Patent number 8,629,535
- Issue date Jan 14, 2014
- GLOBALFOUNDRIES Inc.
- Richard J. Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming a memory cell having a top oxide spacer
- Patent number 8,384,146
- Issue date Feb 26, 2013
- Spansion LLC
- Shenqing Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system with metal and semi-conducting gate
- Patent number 8,283,718
- Issue date Oct 9, 2012
- Spansion LLC
- Angela T. Hui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming a memory cell having a top oxide spacer
- Patent number 8,202,779
- Issue date Jun 19, 2012
- Spansion LLC
- Shenqing Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming narrow structures in a semiconductor device
- Patent number 7,928,005
- Issue date Apr 19, 2011
- Advanced Micro Devices, Inc.
- Michael Brennan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit memory system employing silicon rich layers
- Patent number 7,675,104
- Issue date Mar 9, 2010
- Spansion LLC
- Amol Ramesh Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration approach to form the core floating gate for flash memor...
- Patent number 7,659,166
- Issue date Feb 9, 2010
- GLOBALFOUNDRIES Inc.
- Marina V. Plat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming integrated circuit
- Patent number 7,521,304
- Issue date Apr 21, 2009
- Advanced Micro Devices, Inc.
- Richard J. Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced etching of a high dielectric constant layer
- Patent number 7,498,222
- Issue date Mar 3, 2009
- Advanced Micro Devices, Inc.
- John C. Foster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation region bird's beak suppression
- Patent number 7,465,644
- Issue date Dec 16, 2008
- Advanced Micro Devices, Inc.
- Simon S. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two mask photoresist exposure pattern for dense and isolated regions
- Patent number 7,368,225
- Issue date May 6, 2008
- Advanced Micro Devices, Inc.
- Ramkumar Subramanian
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Etch process for CD reduction of arc material
- Patent number 7,361,588
- Issue date Apr 22, 2008
- Advanced Micro Devices, Inc.
- Phillip L. Jones
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polymer spacers for creating sub-lithographic spaces
- Patent number 7,285,499
- Issue date Oct 23, 2007
- Advanced Micro Devices, Inc.
- Scott A. Bell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for semiconductor gate line dimension reduction
- Patent number 7,268,066
- Issue date Sep 11, 2007
- Advanced Micro Devices, Inc.
- Douglas J. Bonser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patterning with rigid organic under-layer
- Patent number 7,122,455
- Issue date Oct 17, 2006
- Advanced Micro Devices, Inc.
- Christopher F. Lyons
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of multilayer amorphous carbon ARC stack to eliminate line warp...
- Patent number 7,084,071
- Issue date Aug 1, 2006
- Advanced Micro Devices, Inc.
- Srikanteswara Dakshina-Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method using in situ scatterometry to detect photoresist...
- Patent number 7,052,921
- Issue date May 30, 2006
- Advanced Micro Devices, Inc.
- Marina V. Plat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing resist height erosion in a gate etch process
- Patent number 7,005,386
- Issue date Feb 28, 2006
- Advanced Micro Devices, Inc.
- Scott Bell
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SPACER FORMATION WITH STRAIGHT SIDEWALL
- Publication number 20210210610
- Publication date Jul 8, 2021
- CYPRESS SEMICONDUCTOR CORPORATION
- Angela Tai Hui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE
- Publication number 20180358367
- Publication date Dec 13, 2018
- CYPRESS SEMICONDUCTOR CORPORATION
- Scott A. Bell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL DIVISION OF THREE-DIMENSIONAL MEMORY DEVICE
- Publication number 20180323208
- Publication date Nov 8, 2018
- CYPRESS SEMICONDUCTOR CORPORATION
- Rinji Sugino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE
- Publication number 20170162586
- Publication date Jun 8, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Scott BELL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL DIVISION OF THREE-DIMENSIONAL MEMORY DEVICE
- Publication number 20170062456
- Publication date Mar 2, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Rinji Sugino
- G11 - INFORMATION STORAGE
Information Patent Application
Spacer Formation with Straight Sidewall
- Publication number 20170018621
- Publication date Jan 19, 2017
- Angela Tai Hui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buried Hard Mask for Embedded Semiconductor Device Patterning
- Publication number 20160300844
- Publication date Oct 13, 2016
- CYPRESS SEMICONDUCTOR CORPORATION
- Scott A. Bell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE
- Publication number 20160035576
- Publication date Feb 4, 2016
- CYPRESS SEMICONDUCTOR CORPORATION
- Scott BELL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Formation of Gate Sidewall Structure
- Publication number 20150187891
- Publication date Jul 2, 2015
- SPANSION LLC
- Rinji SUGINO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ION IMPLANTATION-ASSISTED ETCH-BACK PROCESS FOR IMPROVING SPACER SH...
- Publication number 20150102400
- Publication date Apr 16, 2015
- SPANSION LLC
- Gong CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Spacer Formation with Straight Sidewall
- Publication number 20150102430
- Publication date Apr 16, 2015
- SPANSION LLC
- Angela Tai Hui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buried Hard Mask for Embedded Semiconductor Device Patterning
- Publication number 20140193972
- Publication date Jul 10, 2014
- SPANSION LLC
- Scott A. BELL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE...
- Publication number 20140117435
- Publication date May 1, 2014
- SPANSION LLC
- Chuan LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit with Metal and Semi-Conducting Gate
- Publication number 20130130487
- Publication date May 23, 2013
- SPANSION LLC
- Angela T. Hui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE...
- Publication number 20120241871
- Publication date Sep 27, 2012
- SPANSION LLC
- Chuan Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER
- Publication number 20120181601
- Publication date Jul 19, 2012
- Shenqing FANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MASK FOR FORMING INTEGRATED CIRCUIT
- Publication number 20120007221
- Publication date Jan 12, 2012
- GLOBALFOUNDRIES INC.
- Richard J. Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER
- Publication number 20110233647
- Publication date Sep 29, 2011
- Shenqing FANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE
- Publication number 20110156130
- Publication date Jun 30, 2011
- Advanced Micro Devices, Inc.
- Michael BRENNAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION APPROACH TO FORM THE CORE FLOATING GATE FOR FLASH MEMOR...
- Publication number 20080254607
- Publication date Oct 16, 2008
- Advanced Micro Devices, Inc.
- Marina V. Plat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH METAL AND SEMI-CONDUCTING GATE
- Publication number 20080142873
- Publication date Jun 19, 2008
- SPANSION LLC
- Angela T. Hui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT MEMORY SYSTEM EMPLOYING SILICON RICH LAYERS
- Publication number 20080023751
- Publication date Jan 31, 2008
- SPANSION LLC
- Amol Ramesh Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming narrow structures in a semiconductor device
- Publication number 20070072437
- Publication date Mar 29, 2007
- Michael Brennan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Etch process for CD reduction of arc material
- Publication number 20060223305
- Publication date Oct 5, 2006
- Advanced Micro Devices, Inc.
- Phillip L. Jones
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REDUCING FEATURE LINE EDGE ROUGHNESS
- Publication number 20060154184
- Publication date Jul 13, 2006
- International Business Machines Corporation
- Arpan P. Mahorowala
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method for semiconductor gate line dimension reduction
- Publication number 20050020019
- Publication date Jan 27, 2005
- Advanced Micro Devices, Inc.
- Douglas J. Bonser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for semiconductor gate line dimension reduction
- Publication number 20040043590
- Publication date Mar 4, 2004
- Advanced Micro Devices, Inc.
- Douglas J. Bonser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for reducing pattern deformation and photoresist poisoning i...
- Publication number 20040023475
- Publication date Feb 5, 2004
- Advanced Micro Devices, Inc.
- Douglas J. Bonser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Notched gate structure fabrication
- Publication number 20020168842
- Publication date Nov 14, 2002
- Khanh Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual damascene using removable via studs
- Publication number 20020164544
- Publication date Nov 7, 2002
- Advanced Micro Devices, Inc.
- Todd P. Luckanc
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Split-gate semiconductor device with L-shaped gate

Split-gate semiconductor device with L-shaped gate

Ion implantation-assisted etch-back process for improving spacer sh...

Buried hard mask for embedded semiconductor device patterning

Split-gate semiconductor device with L-shaped gate

Spacer formation with straight sidewall

Integrating transistors with different poly-silicon heights on the...

Buried hard mask for embedded semiconductor device patterning

Formation of gate sidewall structure

Method for forming narrow structures in a semiconductor device

Integrated circuit with metal and semi-conducting gate

Integrating transistors with different poly-silicon heights on the...

Mask for forming integrated circuit

Methods for forming a memory cell having a top oxide spacer

Integrated circuit system with metal and semi-conducting gate

Methods for forming a memory cell having a top oxide spacer

Method for forming narrow structures in a semiconductor device

Integrated circuit memory system employing silicon rich layers

Integration approach to form the core floating gate for flash memor...

Method for forming integrated circuit

Enhanced etching of a high dielectric constant layer

Isolation region bird's beak suppression

Two mask photoresist exposure pattern for dense and isolated regions

Etch process for CD reduction of arc material

Polymer spacers for creating sub-lithographic spaces

Method for semiconductor gate line dimension reduction

Patterning with rigid organic under-layer

Use of multilayer amorphous carbon ARC stack to eliminate line warp...

System and method using in situ scatterometry to detect photoresist...

Method for reducing resist height erosion in a gate etch process

Patents Applicationslast 30 patents

SPACER FORMATION WITH STRAIGHT SIDEWALL

SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE

VERTICAL DIVISION OF THREE-DIMENSIONAL MEMORY DEVICE

SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE

VERTICAL DIVISION OF THREE-DIMENSIONAL MEMORY DEVICE

Spacer Formation with Straight Sidewall

Buried Hard Mask for Embedded Semiconductor Device Patterning

SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE

Formation of Gate Sidewall Structure

ION IMPLANTATION-ASSISTED ETCH-BACK PROCESS FOR IMPROVING SPACER SH...

Spacer Formation with Straight Sidewall

Buried Hard Mask for Embedded Semiconductor Device Patterning

INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE...

Integrated Circuit with Metal and Semi-Conducting Gate

INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE...

METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER

MASK FOR FORMING INTEGRATED CIRCUIT

METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER

METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE

INTEGRATION APPROACH TO FORM THE CORE FLOATING GATE FOR FLASH MEMOR...

INTEGRATED CIRCUIT SYSTEM WITH METAL AND SEMI-CONDUCTING GATE

INTEGRATED CIRCUIT MEMORY SYSTEM EMPLOYING SILICON RICH LAYERS

Method for forming narrow structures in a semiconductor device

Etch process for CD reduction of arc material

METHOD FOR REDUCING FEATURE LINE EDGE ROUGHNESS

Method for semiconductor gate line dimension reduction

Method for semiconductor gate line dimension reduction

Method for reducing pattern deformation and photoresist poisoning i...

Notched gate structure fabrication

Dual damascene using removable via studs