Scott E. Siers

Person

Elk Grove, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Power reducing logic and non-destructive latch circuits and applica...
- Patent number 9,490,807
- Issue date Nov 8, 2016
- Intel Corporation
- Hon Shing Lau
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power reducing logic and non-destructive latch circuits and applica...
- Patent number 8,421,502
- Issue date Apr 16, 2013
- Intel Corporation
- Hon Shing Lau
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for reducing power consumption in a device using...
- Patent number 8,356,202
- Issue date Jan 15, 2013
- Intel Corporation
- Satish Damaraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell write
- Patent number 8,345,491
- Issue date Jan 1, 2013
- Intel Corporation
- Satish K. Damaraju
- G11 - INFORMATION STORAGE
Information Patent Grant
Power reducing logic and non-destructive latch circuits and applica...
- Patent number 8,305,112
- Issue date Nov 6, 2012
- Intel Corporation
- Hon Shing Lau
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory cell write
- Patent number 8,050,116
- Issue date Nov 1, 2011
- Intel Corporation
- Satish K. Damaraju
- G11 - INFORMATION STORAGE
Information Patent Grant
Processor power consumption control and voltage drop via micro-arch...
- Patent number 8,028,181
- Issue date Sep 27, 2011
- Intel Corporation
- Sanjeev Jahagirdar
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Methods and apparatus for address generation in processors
- Patent number 7,269,711
- Issue date Sep 11, 2007
- Intel Corporation
- Rajesh B. Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual rail time borrowing multiplexer
- Patent number 6,891,400
- Issue date May 10, 2005
- Intel Corporation
- Hans L. Yeager
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Domino circuit topology
- Patent number 6,784,695
- Issue date Aug 31, 2004
- Intel Corporation
- Hans L. Yeager
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
3X adder
- Patent number 6,269,386
- Issue date Jul 31, 2001
- Intel Corporation
- Scott E. Siers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast bi-directional tristateable line driver
- Patent number 6,175,253
- Issue date Jan 16, 2001
- Intel Corporation
- Subramaniam Maiyuran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Booth multiplier for handling variable width operands
- Patent number 6,035,318
- Issue date Mar 7, 2000
- Intel Corporation
- Mohammad Abdallah
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SCALABLE PACKAGE ARCHITECTURE USING RETICLE STITCHING AND PHOTONICS...
- Publication number 20230352464
- Publication date Nov 2, 2023
- Intel Corporation
- Satish Damaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIMULATING DIE ROTATION TO MINIMIZE AREA OVERHEAD OF RETICLE STITCH...
- Publication number 20230205094
- Publication date Jun 29, 2023
- Intel Corporation
- Scott Siers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE ROUTING THROUGH INTRA-CONNECT BRIDGE DIES
- Publication number 20220399277
- Publication date Dec 15, 2022
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER REDUCING LOGIC AND NON-DESTRUCTIVE LATCH CIRCUITS AND APPLICA...
- Publication number 20120223741
- Publication date Sep 6, 2012
- Hon Shing Lau
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROCESSOR POWER CONSUMPTION CONTROL AND VOLTAGE DROP VIA MICRO-ARCH...
- Publication number 20120210105
- Publication date Aug 16, 2012
- Sanjeev Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CELL WRITE
- Publication number 20120039135
- Publication date Feb 16, 2012
- Satish K. Damaraju
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL WRITE
- Publication number 20110069566
- Publication date Mar 24, 2011
- Satish K. Damaraju
- G11 - INFORMATION STORAGE
Information Patent Application
POWER REDUCING LOGIC AND NON-DESTRUCTIVE LATCH CIRCUITS AND APPLICA...
- Publication number 20100289528
- Publication date Nov 18, 2010
- Hon Shing Lau
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Processor power consumption control and voltage drop via micro-arch...
- Publication number 20100077232
- Publication date Mar 25, 2010
- Sanjeev Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A DEVICE USING...
- Publication number 20090249041
- Publication date Oct 1, 2009
- Intel Corporation
- Satish Damaraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power reducing logic and non-destructive latch circuits and applica...
- Publication number 20070103201
- Publication date May 10, 2007
- Hon Shing Lau
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Methods and apparatus for address generation in processors
- Publication number 20050144423
- Publication date Jun 30, 2005
- Intel Corporation
- Rajesh B. Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dual rail time borrowing multiplexer
- Publication number 20040217779
- Publication date Nov 4, 2004
- Intel Corporation
- Hans L. Yeager
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DOMINO CIRCUIT TOPOLOGY
- Publication number 20040164768
- Publication date Aug 26, 2004
- Intel Corporation
- Hans L. Yeager
- H03 - BASIC ELECTRONIC CIRCUITRY

Scott E. Siers

Person

Patents Grantslast 30 patents

Power reducing logic and non-destructive latch circuits and applica...

Power reducing logic and non-destructive latch circuits and applica...

System and method for reducing power consumption in a device using...

Memory cell write

Power reducing logic and non-destructive latch circuits and applica...

Memory cell write

Processor power consumption control and voltage drop via micro-arch...

Methods and apparatus for address generation in processors

Dual rail time borrowing multiplexer

Domino circuit topology

3X adder

Fast bi-directional tristateable line driver

Booth multiplier for handling variable width operands

Patents Applicationslast 30 patents

SCALABLE PACKAGE ARCHITECTURE USING RETICLE STITCHING AND PHOTONICS...

SIMULATING DIE ROTATION TO MINIMIZE AREA OVERHEAD OF RETICLE STITCH...

SELECTIVE ROUTING THROUGH INTRA-CONNECT BRIDGE DIES

POWER REDUCING LOGIC AND NON-DESTRUCTIVE LATCH CIRCUITS AND APPLICA...

PROCESSOR POWER CONSUMPTION CONTROL AND VOLTAGE DROP VIA MICRO-ARCH...

MEMORY CELL WRITE

MEMORY CELL WRITE

POWER REDUCING LOGIC AND NON-DESTRUCTIVE LATCH CIRCUITS AND APPLICA...

Processor power consumption control and voltage drop via micro-arch...

SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A DEVICE USING...

Power reducing logic and non-destructive latch circuits and applica...

Methods and apparatus for address generation in processors

Dual rail time borrowing multiplexer

DOMINO CIRCUIT TOPOLOGY