Scott Irwin

Person

Ames, IA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Chip-to-chip port coherency without overhead
- Patent number 10,084,488
- Issue date Sep 25, 2018
- MoSys, Inc.
- Scott A Irwin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Bootstrapped autonegotiation clock from a referenceless clock chip
- Patent number 10,050,773
- Issue date Aug 14, 2018
- MoSys, Inc.
- Scott A Irwin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PMA RX in coarse loop for high speed sampling
- Patent number 8,391,343
- Issue date Mar 5, 2013
- Xilinx, Inc.
- Jerry Chuang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus to encode and synchronize a serial interface
- Patent number 8,135,037
- Issue date Mar 13, 2012
- MoSys, Inc.
- Charles Boecker
- G11 - INFORMATION STORAGE
Information Patent Grant
MGT/FPGA clock management system
- Patent number 7,885,320
- Issue date Feb 8, 2011
- Xilinx, Inc.
- Eric D. Groen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method of encoding and synchronizing a serial interface
- Patent number 7,599,396
- Issue date Oct 6, 2009
- Magnalynx, Inc.
- Charles Boecker
- G11 - INFORMATION STORAGE
Information Patent Grant
Communication signal testing with a programmable logic device
- Patent number 7,546,499
- Issue date Jun 9, 2009
- Xilinx, Inc.
- Matthew S. Shafer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PMA RX in coarse loop for high speed sampling
- Patent number 7,493,095
- Issue date Feb 17, 2009
- Xilinx, Inc.
- Jerry Chuang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable logic device including programmable multi-gigabit tran...
- Patent number 7,406,118
- Issue date Jul 29, 2008
- Xilinx, Inc.
- Eric D. Groen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
PMA RX in coarse loop for high speed sampling
- Patent number 7,224,951
- Issue date May 29, 2007
- Xilinx, Inc.
- Jerry Chuang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Communication signal testing with a programmable logic device
- Patent number 7,188,283
- Issue date Mar 6, 2007
- Xilinx, Inc.
- Matthew S. Shafer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system and memory device having a serial interface
- Patent number 7,167,410
- Issue date Jan 23, 2007
- Magnalynx
- Charles Boecker
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with auto negotiation
- Patent number 6,976,102
- Issue date Dec 13, 2005
- Xilinx, Inc.
- Eric D. Groen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS TO ENCODE AND SYNCHRONIZE A SERIAL INTERFACE
- Publication number 20090316728
- Publication date Dec 24, 2009
- MagnaLynx, Inc.
- Charles Boecker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PMA RX in course loop for high speed sampling
- Publication number 20070201541
- Publication date Aug 30, 2007
- Xilinx, Inc.
- Jerry Chuang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method of encoding and synchronizing a serial interface
- Publication number 20070008992
- Publication date Jan 11, 2007
- MagnaLynx, Inc.
- Charles Boecker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Memory system and memory device having a serial interface
- Publication number 20060239107
- Publication date Oct 26, 2006
- MagnaLynx, Inc.
- Charles Boecker
- G11 - INFORMATION STORAGE
Information Patent Application
Programmable logic device including programmable multi-gigabit tran...
- Publication number 20050058187
- Publication date Mar 17, 2005
- Xilinx, Inc.
- Eric D. Groen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Scott Irwin

Person

Patents Grantslast 30 patents

Chip-to-chip port coherency without overhead

Bootstrapped autonegotiation clock from a referenceless clock chip

PMA RX in coarse loop for high speed sampling

Method and apparatus to encode and synchronize a serial interface

MGT/FPGA clock management system

Method of encoding and synchronizing a serial interface

Communication signal testing with a programmable logic device

PMA RX in coarse loop for high speed sampling

Programmable logic device including programmable multi-gigabit tran...

PMA RX in coarse loop for high speed sampling

Communication signal testing with a programmable logic device

Memory system and memory device having a serial interface

Integrated circuit with auto negotiation

Patents Applicationslast 30 patents

METHOD AND APPARATUS TO ENCODE AND SYNCHRONIZE A SERIAL INTERFACE

PMA RX in course loop for high speed sampling

Method of encoding and synchronizing a serial interface

Memory system and memory device having a serial interface

Programmable logic device including programmable multi-gigabit tran...