Scott Thompson

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
CMOS fabrication process utilizing special transistor orientation
- Patent number 7,888,710
- Issue date Feb 15, 2011
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS fabrication process utilizing special transistor orientation
- Patent number 7,312,485
- Issue date Dec 25, 2007
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nitrogen controlled growth of dislocation loop in stress enhanced t...
- Patent number 7,226,824
- Issue date Jun 5, 2007
- Intel Corporation
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nitrogen controlled growth of dislocation loop in stress enhanced t...
- Patent number 7,187,057
- Issue date Mar 6, 2007
- Intel Corporation
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nitrogen controlled growth of dislocation loop in stress enhanced t...
- Patent number 6,800,887
- Issue date Oct 5, 2004
- Intel Corporation
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and process flow for fabrication of dual gate floating bo...
- Patent number 6,624,032
- Issue date Sep 23, 2003
- Intel Corporation
- Mohsen Alavi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with borderless contacts
- Patent number 6,515,351
- Issue date Feb 4, 2003
- Intel Corporation
- Mohamed Arafa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and process flow for fabrication of dual gate floating bo...
- Patent number 6,392,271
- Issue date May 21, 2002
- Intel Corporation
- Mohsen Alavi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with insulating spacers separating borderless co...
- Patent number 6,294,823
- Issue date Sep 25, 2001
- Intel Corporation
- Mohamed Arafa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with borderless contacts
- Patent number 6,228,777
- Issue date May 8, 2001
- Intel Corporation
- Mohamed Arafa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Channel dopant implantation with automatic compensation for variati...
- Patent number 6,020,244
- Issue date Feb 1, 2000
- Intel Corporation
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low damage doping technique for self-aligned source and drain regions
- Patent number 5,976,939
- Issue date Nov 2, 1999
- Intel Corporation
- Scott Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming doped regions from solid phase diffusion source
- Patent number 5,877,072
- Issue date Mar 2, 1999
- Intel Corporation
- Ebrahim Andideh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two step source/drain anneal to prevent dopant evaporation
- Patent number 5,874,344
- Issue date Feb 23, 1999
- Intel Corporation
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CMOS FABRICATION PROCESS UTILIZING SPECIAL TRANSISTOR ORIENTATION
- Publication number 20080036005
- Publication date Feb 14, 2008
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Nitrogen controlled growth of dislocation loop in stress enhanced t...
- Publication number 20050017309
- Publication date Jan 27, 2005
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Nitrogen controlled growth of dislocation loop in stress enhanced t...
- Publication number 20050014351
- Publication date Jan 20, 2005
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NITROGEN CONTROLLED GROWTH OF DISLOCATION LOOP IN STRESS ENHANCED T...
- Publication number 20040191975
- Publication date Sep 30, 2004
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure and process flow for fabrication of dual gate floating bo...
- Publication number 20020098657
- Publication date Jul 25, 2002
- Mohsen Alavi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS fabrication process utilizing special transistor orientation
- Publication number 20020063292
- Publication date May 30, 2002
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND PROCESS FLOW FOR FABRICATION OF DUAL GATE FLOATING BO...
- Publication number 20020034853
- Publication date Mar 21, 2002
- MOHSEN ALAVI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit with borderless contacts
- Publication number 20010019898
- Publication date Sep 6, 2001
- Mohamed Arafa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating a supply decoupling capacitor
- Publication number 20010009785
- Publication date Jul 26, 2001
- Mohamed Arafa
- H01 - BASIC ELECTRIC ELEMENTS

Scott Thompson

Person

Patents Grantslast 30 patents

CMOS fabrication process utilizing special transistor orientation

CMOS fabrication process utilizing special transistor orientation

Nitrogen controlled growth of dislocation loop in stress enhanced t...

Nitrogen controlled growth of dislocation loop in stress enhanced t...

Nitrogen controlled growth of dislocation loop in stress enhanced t...

Structure and process flow for fabrication of dual gate floating bo...

Integrated circuit with borderless contacts

Structure and process flow for fabrication of dual gate floating bo...

Integrated circuit with insulating spacers separating borderless co...

Integrated circuit with borderless contacts

Channel dopant implantation with automatic compensation for variati...

Low damage doping technique for self-aligned source and drain regions

Process for forming doped regions from solid phase diffusion source

Two step source/drain anneal to prevent dopant evaporation

Patents Applicationslast 30 patents

CMOS FABRICATION PROCESS UTILIZING SPECIAL TRANSISTOR ORIENTATION

Nitrogen controlled growth of dislocation loop in stress enhanced t...

Nitrogen controlled growth of dislocation loop in stress enhanced t...

NITROGEN CONTROLLED GROWTH OF DISLOCATION LOOP IN STRESS ENHANCED T...

Structure and process flow for fabrication of dual gate floating bo...

CMOS fabrication process utilizing special transistor orientation

STRUCTURE AND PROCESS FLOW FOR FABRICATION OF DUAL GATE FLOATING BO...

Integrated circuit with borderless contacts

Method of fabricating a supply decoupling capacitor