Se Young Yang

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 12,211,821
- Issue date Jan 28, 2025
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 11,735,563
- Issue date Aug 22, 2023
- Invensas LLC
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 11,189,595
- Issue date Nov 30, 2021
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 10,756,049
- Issue date Aug 25, 2020
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D thin profile pre-stacking architecture using reconstitution method
- Patent number 10,181,455
- Issue date Jan 15, 2019
- Apple Inc.
- Jun Zhai
- G11 - INFORMATION STORAGE
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 9,761,558
- Issue date Sep 12, 2017
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double side mounting memory integration in thin low warpage fanout...
- Patent number 9,659,907
- Issue date May 23, 2017
- Apple Inc.
- Jun Zhai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System in package fan out stacking architecture and process flow
- Patent number 9,633,974
- Issue date Apr 25, 2017
- Apple Inc.
- Jun Zhai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin wafer handling and known good die test method
- Patent number 9,601,398
- Issue date Mar 21, 2017
- Invensas Corporation
- Charles G. Woychik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 9,252,122
- Issue date Feb 2, 2016
- Invensas Corporation
- Ellis Chau
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
EMI shielded wafer level fan-out pop package
- Patent number 9,236,355
- Issue date Jan 12, 2016
- Apple Inc.
- Jun Zhai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 9,105,483
- Issue date Aug 11, 2015
- Invensas Corporation
- Ellis Chau
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 9,041,227
- Issue date May 26, 2015
- Invensas Corporation
- Ellis Chau
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
TSV fabrication using a removable handling structure
- Patent number 8,978,247
- Issue date Mar 17, 2015
- Invensas Corporation
- Se Young Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin wafer handling and known good die test method
- Patent number 8,846,447
- Issue date Sep 30, 2014
- Invensas Corporation
- Charles G. Woychik
- G01 - MEASURING TESTING
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 8,836,136
- Issue date Sep 16, 2014
- Invensas Corporation
- Ellis Chau
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Package-on-package assembly with wire bond vias
- Patent number 8,404,520
- Issue date Mar 26, 2013
- Invensas Corporation
- Ellis Chau
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20240055393
- Publication date Feb 15, 2024
- Invensas LLC
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20220165703
- Publication date May 26, 2022
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Package-on-package Assembly With Wire Bond Vias
- Publication number 20210035948
- Publication date Feb 4, 2021
- Invensas Corporation
- Ellis Chau
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Application
3D THIN PROFILE PRE-STACKING ARCHITECTURE USING RECONSTITUTION METHOD
- Publication number 20180204820
- Publication date Jul 19, 2018
- Apple Inc.
- Jun Zhai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20180026007
- Publication date Jan 25, 2018
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE SIDE MOUNTING MEMORY INTEGRATION IN THIN LOW WARPAGE FANOUT...
- Publication number 20160300813
- Publication date Oct 13, 2016
- Apple Inc.
- Jun Zhai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM IN PACKAGE FAN OUT STACKING ARCHITECTURE AND PROCESS FLOW
- Publication number 20160260684
- Publication date Sep 8, 2016
- Apple Inc.
- Jun Zhai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECONFIGURED WIDE I/O MEMORY MODULES AND PACKAGE ARCHITECTURES USIN...
- Publication number 20150364454
- Publication date Dec 17, 2015
- Apple Inc.
- Jun Zhai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMI SHIELDED WAFER LEVEL FAN-OUT POP PACKAGE
- Publication number 20150303149
- Publication date Oct 22, 2015
- Jun Zhai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20150255424
- Publication date Sep 10, 2015
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thin Wafer Handling and Known Good Die Test Method
- Publication number 20150014688
- Publication date Jan 15, 2015
- Invensas Corporation
- Charles G. Woychik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THIN WAFER HANDLING AND KNOWN GOOD DIE TEST METHOD
- Publication number 20140054763
- Publication date Feb 27, 2014
- Invensas Corporation
- Charles G. Woychik
- G01 - MEASURING TESTING
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20130328219
- Publication date Dec 12, 2013
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TSV FABRICATION USING A REMOVABLE HANDLING STRUCTURE
- Publication number 20130313012
- Publication date Nov 28, 2013
- Invensas Corporation
- Se Young Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20130200533
- Publication date Aug 8, 2013
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20130095610
- Publication date Apr 18, 2013
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20130093087
- Publication date Apr 18, 2013
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
- Publication number 20130093088
- Publication date Apr 18, 2013
- Invensas Corporation
- Ellis Chau
- H01 - BASIC ELECTRIC ELEMENTS

Se Young Yang

Person

Patents Grantslast 30 patents

Package-on-package assembly with wire bond vias

Package-on-package assembly with wire bond vias

Package-on-package assembly with wire bond vias

Package-on-package assembly with wire bond vias

3D thin profile pre-stacking architecture using reconstitution method

Package-on-package assembly with wire bond vias

Double side mounting memory integration in thin low warpage fanout...

System in package fan out stacking architecture and process flow

Thin wafer handling and known good die test method

Package-on-package assembly with wire bond vias

EMI shielded wafer level fan-out pop package

Package-on-package assembly with wire bond vias

Package-on-package assembly with wire bond vias

TSV fabrication using a removable handling structure

Thin wafer handling and known good die test method

Package-on-package assembly with wire bond vias

Package-on-package assembly with wire bond vias

Patents Applicationslast 30 patents

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

Package-on-package Assembly With Wire Bond Vias

3D THIN PROFILE PRE-STACKING ARCHITECTURE USING RECONSTITUTION METHOD

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

DOUBLE SIDE MOUNTING MEMORY INTEGRATION IN THIN LOW WARPAGE FANOUT...

SYSTEM IN PACKAGE FAN OUT STACKING ARCHITECTURE AND PROCESS FLOW

RECONFIGURED WIDE I/O MEMORY MODULES AND PACKAGE ARCHITECTURES USIN...

EMI SHIELDED WAFER LEVEL FAN-OUT POP PACKAGE

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

Thin Wafer Handling and Known Good Die Test Method

THIN WAFER HANDLING AND KNOWN GOOD DIE TEST METHOD

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

TSV FABRICATION USING A REMOVABLE HANDLING STRUCTURE

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS