Sean O. Stalley

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Non-posted write transactions for a computer bus
- Patent number 12,332,813
- Issue date Jun 17, 2025
- Intel Corporation
- Rajesh M. Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and apparatus for SRIS mode selection for PCIE
- Patent number 12,135,581
- Issue date Nov 5, 2024
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and apparatus for SRIS mode selection for PCIe
- Patent number 11,630,480
- Issue date Apr 18, 2023
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Predictive packet header compression
- Patent number 11,593,280
- Issue date Feb 28, 2023
- Intel Corporation
- Sean O. Stalley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-posted write transactions for a computer bus
- Patent number 11,513,979
- Issue date Nov 29, 2022
- Intel Corporation
- Rajesh M. Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-posted write transactions for a computer bus
- Patent number 10,970,238
- Issue date Apr 6, 2021
- Intel Corporation
- Rajesh M. Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for software defined interconnect switch
- Patent number 10,191,877
- Issue date Jan 29, 2019
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method to increase throughput of a transmitter
- Patent number 9,680,758
- Issue date Jun 13, 2017
- Intel Corporation
- Sean O. Stalley
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
NON-POSTED WRITE TRANSACTIONS FOR A COMPUTER BUS
- Publication number 20230035420
- Publication date Feb 2, 2023
- Intel Corporation
- Rajesh M. Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, METHOD, AND APPARATUS FOR SRIS MODE SELECTION FOR PCIE
- Publication number 20230022948
- Publication date Jan 26, 2023
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-POSTED WRITE TRANSACTIONS FOR A COMPUTER BUS
- Publication number 20210209037
- Publication date Jul 8, 2021
- Intel Corporation
- Rajesh M. Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-POSTED WRITE TRANSACTIONS
- Publication number 20200004703
- Publication date Jan 2, 2020
- Intel Corporation
- Rajesh M. Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREDICTIVE PACKET HEADER COMPRESSION
- Publication number 20190391936
- Publication date Dec 26, 2019
- Intel Corporation
- Sean O. Stalley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, METHOD, AND APPARATUS FOR SRIS MODE SELECTION FOR PCIE
- Publication number 20190041898
- Publication date Feb 7, 2019
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTION STATES OF A DEVICE COUPLED TO A COMPUTER BUS
- Publication number 20180300264
- Publication date Oct 18, 2018
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR SOFTWARE DEFINED INTERCONNECT SWITCH
- Publication number 20170177528
- Publication date Jun 22, 2017
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD TO INCREASE THROUGHPUT OF A TRANSMITTER
- Publication number 20170063508
- Publication date Mar 2, 2017
- Intel Corporation
- Sean O. Stalley
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
BANDWIDTH ALLOCATION IN A NETWORKED ENVIRONMENT
- Publication number 20150149639
- Publication date May 28, 2015
- Abdul Hawk Ismail
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Sean O. Stalley

Person

Patents Grantslast 30 patents

Non-posted write transactions for a computer bus

System, method, and apparatus for SRIS mode selection for PCIE

System, method, and apparatus for SRIS mode selection for PCIe

Predictive packet header compression

Non-posted write transactions for a computer bus

Non-posted write transactions for a computer bus

Architecture for software defined interconnect switch

Apparatus and method to increase throughput of a transmitter

Patents Applicationslast 30 patents

NON-POSTED WRITE TRANSACTIONS FOR A COMPUTER BUS

SYSTEM, METHOD, AND APPARATUS FOR SRIS MODE SELECTION FOR PCIE

NON-POSTED WRITE TRANSACTIONS FOR A COMPUTER BUS

NON-POSTED WRITE TRANSACTIONS

PREDICTIVE PACKET HEADER COMPRESSION

SYSTEM, METHOD, AND APPARATUS FOR SRIS MODE SELECTION FOR PCIE

FUNCTION STATES OF A DEVICE COUPLED TO A COMPUTER BUS

ARCHITECTURE FOR SOFTWARE DEFINED INTERCONNECT SWITCH

APPARATUS AND METHOD TO INCREASE THROUGHPUT OF A TRANSMITTER

BANDWIDTH ALLOCATION IN A NETWORKED ENVIRONMENT