Sebastian Winkel

Person

Los Altos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems, methods and apparatus for speculative elimination of load...
- Patent number 12,169,718
- Issue date Dec 17, 2024
- Intel Corporation
- Vineeth Thamarassery Mekkat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-stage automatic compilation for vector computations in applic...
- Patent number 11,934,809
- Issue date Mar 19, 2024
- Intel Corporation
- Junyong Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for predication and implicit destination
- Patent number 10,884,735
- Issue date Jan 5, 2021
- Intel Corporation
- Jayesh Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods to assign a logical thread to a physical th...
- Patent number 10,877,765
- Issue date Dec 29, 2020
- Intel Corporation
- Sebastian Winkel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for supporting speculative memory optimizations
- Patent number 10,853,078
- Issue date Dec 1, 2020
- Intel Corporation
- Vineeth Mekkat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Eliminating redundant stores using a protection designator and a cl...
- Patent number 10,540,178
- Issue date Jan 21, 2020
- Intel Corporation
- Vineeth Mekkat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing partial register write operations in a processor
- Patent number 10,346,170
- Issue date Jul 9, 2019
- Intel Corporation
- Jayesh Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware apparatuses and methods to fuse instructions
- Patent number 10,324,724
- Issue date Jun 18, 2019
- Intel Corporation
- Patrick P. Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supporting binary translation alias detection in an out-of-order pr...
- Patent number 10,228,956
- Issue date Mar 12, 2019
- Intel Corporation
- Vineeth Mekkat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fused adjacent memory stores
- Patent number 10,216,516
- Issue date Feb 26, 2019
- Intel Corporation
- Sebastian Winkel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for efficient register allocation and reclamation
- Patent number 10,083,033
- Issue date Sep 25, 2018
- Intel Corporation
- Sebastian Winkel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for scheduling instructions
- Patent number 10,055,256
- Issue date Aug 21, 2018
- Intel Corporation
- Sebastian Winkel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for recovering from bad store-to-load forwardi...
- Patent number 9,996,356
- Issue date Jun 12, 2018
- Intel Corporation
- Vineeth Mekkat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for predication and implicit destination
- Patent number 9,904,546
- Issue date Feb 27, 2018
- Intel Corporation
- Jayesh Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for memory aliasing detection in an out-of-ord...
- Patent number 9,710,389
- Issue date Jul 18, 2017
- Intel Corporation
- Oleg Margulis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for memory disambiguation in an out-of-order...
- Patent number 9,524,170
- Issue date Dec 20, 2016
- Intel Corporation
- Rainer Theur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for scheduling instructions
- Patent number 9,274,799
- Issue date Mar 1, 2016
- Intel Corporation
- Sebastian Winkel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling of binary translated self modifying code and cross modifyi...
- Patent number 9,116,729
- Issue date Aug 25, 2015
- Intel Corporation
- Nirajan L. Cooray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transitioning from source instruction set architecture (ISA) code t...
- Patent number 8,775,153
- Issue date Jul 8, 2014
- Intel Corporation
- Sebastian Winkel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transitioning from source instruction set architecture (ISA) code t...
- Patent number 8,762,127
- Issue date Jun 24, 2014
- Intel Corporation
- Sebastian Winkel
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INSTRUCTIONS AND SUPPORT FOR CONDITIONAL COMPARISON AND TEST
- Publication number 20240220262
- Publication date Jul 4, 2024
- Jason AGRON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFIX EXTENSIONS FOR EXTENDED GENERAL PURPOSE REGISTERS WITH OPTIM...
- Publication number 20240220260
- Publication date Jul 4, 2024
- Jason AGRON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS AND SUPPORT FOR STACK PUSH AND POP
- Publication number 20240220257
- Publication date Jul 4, 2024
- Jason AGRON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS AND SUPPORT FOR CONDITIONAL LOAD AND STORE
- Publication number 20240220261
- Publication date Jul 4, 2024
- Jason AGRON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performance Monitoring Emulation in Translated Branch Instructions...
- Publication number 20230315501
- Publication date Oct 5, 2023
- Intel Corporation
- Sebastian Winkel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-STAGE AUTOMATIC COMPILATION FOR VECTOR COMPUTATIONS IN APPLIC...
- Publication number 20230102562
- Publication date Mar 30, 2023
- Intel Corporation
- Junyong Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technology For Optimizing Memory-To-Register Operations
- Publication number 20220413870
- Publication date Dec 29, 2022
- Intel Corporation
- Vineeth Thamarassery Mekkat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE PROFILER TO TRACK INSTRUCTION SEQUENCE INFORMATION INCLUDI...
- Publication number 20200210193
- Publication date Jul 2, 2020
- Intel Corporation
- Sangeeta BHATTACHARYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SUPPORTING SPECULATIVE MEMORY OPTIMIZATIONS
- Publication number 20200201645
- Publication date Jun 25, 2020
- Intel Corporation
- Vineeth MEKKAT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSLATION TABLE ENTRY PREFETCHING IN DYNAMIC BINARY TRANSLATION B...
- Publication number 20190179766
- Publication date Jun 13, 2019
- Intel Corporation
- Girish Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR PREDICATION AND IMPLICIT DESTINATION
- Publication number 20190042247
- Publication date Feb 7, 2019
- Intel Corporation
- Jayesh Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUSED ADJACENT MEMORY STORES
- Publication number 20180095761
- Publication date Apr 5, 2018
- Intel Corporation
- Sebastian Winkel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING BINARY TRANSLATION ALIAS DETECTION IN AN OUT-OF-ORDER PR...
- Publication number 20180095765
- Publication date Apr 5, 2018
- Vineeth Mekkat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Logic for Dynamic Store Elimination
- Publication number 20180074827
- Publication date Mar 15, 2018
- Intel Corporation
- Vineeth Mekkat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for recovering from bad store-to-load forwardi...
- Publication number 20170185404
- Publication date Jun 29, 2017
- Vineeth Mekkat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE APPARATUSES AND METHODS TO FUSE INSTRUCTIONS
- Publication number 20170177343
- Publication date Jun 22, 2017
- Patrick P. Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Logic for Predication and Implicit Destination
- Publication number 20160378472
- Publication date Dec 29, 2016
- Intel Corporation
- Jayesh Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING PARTIAL REGISTER WRITE OPERATIONS IN A PROCESSOR
- Publication number 20160328239
- Publication date Nov 10, 2016
- Intel Corporation
- Jayesh Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS TO SELECTIVELY EXECUTE A COMMIT INSTRUCTION
- Publication number 20160283247
- Publication date Sep 29, 2016
- Intel Corporation
- Girish Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR SCHEDULING INSTRUCTIONS
- Publication number 20160274944
- Publication date Sep 22, 2016
- Intel Corporation
- Sebastian Winkel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR MEMORY ALIASING DETECTION IN AN OUT-OF-ORD...
- Publication number 20160267009
- Publication date Sep 15, 2016
- Oleg Margulis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS TO ASSIGN A LOGICAL THREAD TO A PHYSICAL TH...
- Publication number 20160266905
- Publication date Sep 15, 2016
- Intel Corporation
- Sebastian Winkel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR EFFICIENT REGISTER ALLOCATION AND RECLAMATION
- Publication number 20160266901
- Publication date Sep 15, 2016
- SEBASTIAN WINKEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING AND MAINTAINING A STACK OF PR...
- Publication number 20160179538
- Publication date Jun 23, 2016
- Intel Corporation
- JAMISON D. COLLINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC TO PERFORM A FUSED SINGLE CYCLE INCREMENT-COM...
- Publication number 20160179542
- Publication date Jun 23, 2016
- Patrick P. Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR SCHEDULING INSTRUCTIONS
- Publication number 20160085556
- Publication date Mar 24, 2016
- Intel Corporation
- Sebastian Winkel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Logic for Memory Disambiguation in an Out-of-Order...
- Publication number 20150178090
- Publication date Jun 25, 2015
- Rainer Theuer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HANDLING OF BINARY TRANSLATED SELF MODIFYING CODE AND CROSS MODIFYI...
- Publication number 20140189659
- Publication date Jul 3, 2014
- Nirajan L. Cooray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSITIONING FROM SOURCE INSTRUCTION SET ARCHITECTURE (ISA) CODE T...
- Publication number 20130198458
- Publication date Aug 1, 2013
- SEBASTIAN WINKEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transitioning From Source Instruction Set Architecture (ISA) Code T...
- Publication number 20110153307
- Publication date Jun 23, 2011
- Sebastian Winkel
- G06 - COMPUTING CALCULATING COUNTING

Sebastian Winkel

Person

Patents Grantslast 30 patents

Systems, methods and apparatus for speculative elimination of load...

Multi-stage automatic compilation for vector computations in applic...

Instruction and logic for predication and implicit destination

Apparatuses and methods to assign a logical thread to a physical th...

Method and apparatus for supporting speculative memory optimizations

Eliminating redundant stores using a protection designator and a cl...

Performing partial register write operations in a processor

Hardware apparatuses and methods to fuse instructions

Supporting binary translation alias detection in an out-of-order pr...

Fused adjacent memory stores

Apparatus and method for efficient register allocation and reclamation

Instruction and logic for scheduling instructions

Method and apparatus for recovering from bad store-to-load forwardi...

Instruction and logic for predication and implicit destination

Method and apparatus for memory aliasing detection in an out-of-ord...

Instruction and logic for memory disambiguation in an out-of-order...

Instruction and logic for scheduling instructions

Handling of binary translated self modifying code and cross modifyi...

Transitioning from source instruction set architecture (ISA) code t...

Transitioning from source instruction set architecture (ISA) code t...

Patents Applicationslast 30 patents

INSTRUCTIONS AND SUPPORT FOR CONDITIONAL COMPARISON AND TEST

PREFIX EXTENSIONS FOR EXTENDED GENERAL PURPOSE REGISTERS WITH OPTIM...

INSTRUCTIONS AND SUPPORT FOR STACK PUSH AND POP

INSTRUCTIONS AND SUPPORT FOR CONDITIONAL LOAD AND STORE

Performance Monitoring Emulation in Translated Branch Instructions...

MULTI-STAGE AUTOMATIC COMPILATION FOR VECTOR COMPUTATIONS IN APPLIC...

Technology For Optimizing Memory-To-Register Operations

HARDWARE PROFILER TO TRACK INSTRUCTION SEQUENCE INFORMATION INCLUDI...

METHOD AND APPARATUS FOR SUPPORTING SPECULATIVE MEMORY OPTIMIZATIONS

TRANSLATION TABLE ENTRY PREFETCHING IN DYNAMIC BINARY TRANSLATION B...

INSTRUCTION AND LOGIC FOR PREDICATION AND IMPLICIT DESTINATION

FUSED ADJACENT MEMORY STORES

SUPPORTING BINARY TRANSLATION ALIAS DETECTION IN AN OUT-OF-ORDER PR...

Instruction and Logic for Dynamic Store Elimination

Method and apparatus for recovering from bad store-to-load forwardi...

HARDWARE APPARATUSES AND METHODS TO FUSE INSTRUCTIONS

Instruction and Logic for Predication and Implicit Destination

PERFORMING PARTIAL REGISTER WRITE OPERATIONS IN A PROCESSOR

APPARATUSES AND METHODS TO SELECTIVELY EXECUTE A COMMIT INSTRUCTION

INSTRUCTION AND LOGIC FOR SCHEDULING INSTRUCTIONS

METHOD AND APPARATUS FOR MEMORY ALIASING DETECTION IN AN OUT-OF-ORD...

APPARATUSES AND METHODS TO ASSIGN A LOGICAL THREAD TO A PHYSICAL TH...

APPARATUS AND METHOD FOR EFFICIENT REGISTER ALLOCATION AND RECLAMATION

METHOD AND APPARATUS FOR IMPLEMENTING AND MAINTAINING A STACK OF PR...

INSTRUCTION AND LOGIC TO PERFORM A FUSED SINGLE CYCLE INCREMENT-COM...

INSTRUCTION AND LOGIC FOR SCHEDULING INSTRUCTIONS

Instruction and Logic for Memory Disambiguation in an Out-of-Order...

HANDLING OF BINARY TRANSLATED SELF MODIFYING CODE AND CROSS MODIFYI...

TRANSITIONING FROM SOURCE INSTRUCTION SET ARCHITECTURE (ISA) CODE T...

Transitioning From Source Instruction Set Architecture (ISA) Code T...