Seiichi Aritome

Person

Hsinchu, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Program and read trim setting
- Patent number 10,109,351
- Issue date Oct 23, 2018
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Program and read trim setting
- Patent number 9,508,440
- Issue date Nov 29, 2016
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile multilevel memory cells
- Patent number 9,070,450
- Issue date Jun 30, 2015
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Adjusting program and erase voltages in a memory device
- Patent number 9,030,874
- Issue date May 12, 2015
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, apparatus, and system for improved read operation in memory
- Patent number 8,897,078
- Issue date Nov 25, 2014
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell operation
- Patent number 8,787,090
- Issue date Jul 22, 2014
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
Adjusting program and erase voltages in a memory device
- Patent number 8,634,244
- Issue date Jan 21, 2014
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile multilevel memory cells
- Patent number 8,611,152
- Issue date Dec 17, 2013
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
NAND with back biased operation
- Patent number 8,493,790
- Issue date Jul 23, 2013
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with both single and multiple level cells
- Patent number 8,437,186
- Issue date May 7, 2013
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Operating memory cells
- Patent number 8,427,880
- Issue date Apr 23, 2013
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile multilevel memory cell programming
- Patent number 8,369,147
- Issue date Feb 5, 2013
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple select gates with non-volatile memory cells
- Patent number 8,305,810
- Issue date Nov 6, 2012
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Sensing memory cells
- Patent number 8,264,879
- Issue date Sep 11, 2012
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Multilevel memory cell operation
- Patent number 8,238,155
- Issue date Aug 7, 2012
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory voltage cycle adjustment
- Patent number 8,238,167
- Issue date Aug 7, 2012
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory read methods, apparatus, and systems
- Patent number 8,228,742
- Issue date Jul 24, 2012
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with both single and multiple level cells
- Patent number 8,199,572
- Issue date Jun 12, 2012
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduction of punch-through disturb during programming of a memory d...
- Patent number 8,164,950
- Issue date Apr 24, 2012
- Micron Technology, Inc.
- Alessandro Torsi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell programming
- Patent number 8,154,926
- Issue date Apr 10, 2012
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, apparatus, and system for erasing memory
- Patent number 8,120,954
- Issue date Feb 21, 2012
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory cell read failure reduction
- Patent number 8,116,135
- Issue date Feb 14, 2012
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell operation
- Patent number 8,116,137
- Issue date Feb 14, 2012
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile multilevel memory cells
- Patent number 8,102,707
- Issue date Jan 24, 2012
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
NAND with back biased operation
- Patent number 8,072,814
- Issue date Dec 6, 2011
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell programming
- Patent number 8,069,382
- Issue date Nov 29, 2011
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory read methods, apparatus, and systems
- Patent number 8,018,778
- Issue date Sep 13, 2011
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with both single and multiple level cells
- Patent number 8,000,136
- Issue date Aug 16, 2011
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple select gates with non-volatile memory cells
- Patent number 7,995,391
- Issue date Aug 9, 2011
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory voltage cycle adjustment
- Patent number 7,983,090
- Issue date Jul 19, 2011
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
PROGRAM AND READ TRIM SETTING
- Publication number 20170053701
- Publication date Feb 23, 2017
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAM AND READ TRIM SETTING
- Publication number 20150221378
- Publication date Aug 6, 2015
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MULTILEVEL MEMORY CELLS
- Publication number 20140160843
- Publication date Jun 12, 2014
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS
- Publication number 20120257451
- Publication date Oct 11, 2012
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL OPERATION
- Publication number 20120140569
- Publication date Jun 7, 2012
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MULTILEVEL MEMORY CELLS
- Publication number 20120106248
- Publication date May 3, 2012
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
NAND WITH BACK BIASED OPERATION
- Publication number 20120069680
- Publication date Mar 22, 2012
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS
- Publication number 20110273932
- Publication date Nov 10, 2011
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY VOLTAGE CYCLE ADJUSTMENT
- Publication number 20110255342
- Publication date Oct 20, 2011
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
MULTIPLE SELECT GATES WITH NON-VOLATILE MEMORY CELLS
- Publication number 20110249494
- Publication date Oct 13, 2011
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL OPERATION
- Publication number 20110164455
- Publication date Jul 7, 2011
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL PROGRAMMING
- Publication number 20110083050
- Publication date Apr 7, 2011
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
SENSING MEMORY CELLS
- Publication number 20110058417
- Publication date Mar 10, 2011
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY CELL READ FAILURE REDUCTION
- Publication number 20110047422
- Publication date Feb 24, 2011
- Micron Technology, Inc.
- Seiichi Aritome
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE SELECT GATES WITH NON-VOLATILE MEMORY CELLS
- Publication number 20100323480
- Publication date Dec 23, 2010
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
OPERATING MEMORY CELLS
- Publication number 20100290289
- Publication date Nov 18, 2010
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS
- Publication number 20100277981
- Publication date Nov 4, 2010
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MULTILEVEL MEMORY CELLS
- Publication number 20100226177
- Publication date Sep 9, 2010
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
NAND WITH BACK BIASED OPERATION
- Publication number 20100220528
- Publication date Sep 2, 2010
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY VOLTAGE CYCLE ADJUSTMENT
- Publication number 20100188904
- Publication date Jul 29, 2010
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING
- Publication number 20100182832
- Publication date Jul 22, 2010
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
MULTILEVEL MEMORY CELL OPERATION
- Publication number 20100142274
- Publication date Jun 10, 2010
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL PROGRAMMING
- Publication number 20100128528
- Publication date May 27, 2010
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING
- Publication number 20100020605
- Publication date Jan 28, 2010
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY CELL READ FAILURE REDUCTION
- Publication number 20100014352
- Publication date Jan 21, 2010
- Micron Technology, Inc.
- Seiichi Aritome
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NAND WITH BACK BIASED OPERATION
- Publication number 20090279359
- Publication date Nov 12, 2009
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES HAVING REDUCED WORD LINE CURRENT AND METHOD OF OPERA...
- Publication number 20090147588
- Publication date Jun 11, 2009
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
Adjusting program and erase voltages in a memory device
- Publication number 20090147582
- Publication date Jun 11, 2009
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR ERASING MEMORY
- Publication number 20090147572
- Publication date Jun 11, 2009
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY READ METHODS, APPARATUS, AND SYSTEMS
- Publication number 20090135654
- Publication date May 28, 2009
- Micron Technology, Inc.
- Seiichi Aritome
- G11 - INFORMATION STORAGE

Seiichi Aritome

Person

Patents Grantslast 30 patents

Program and read trim setting

Program and read trim setting

Non-volatile multilevel memory cells

Adjusting program and erase voltages in a memory device

Method, apparatus, and system for improved read operation in memory

Memory cell operation

Adjusting program and erase voltages in a memory device

Non-volatile multilevel memory cells

NAND with back biased operation

Non-volatile memory with both single and multiple level cells

Operating memory cells

Non-volatile multilevel memory cell programming

Multiple select gates with non-volatile memory cells

Sensing memory cells

Multilevel memory cell operation

Memory voltage cycle adjustment

Memory read methods, apparatus, and systems

Non-volatile memory with both single and multiple level cells

Reduction of punch-through disturb during programming of a memory d...

Memory cell programming

Method, apparatus, and system for erasing memory

Non-volatile memory cell read failure reduction

Memory cell operation

Non-volatile multilevel memory cells

NAND with back biased operation

Memory cell programming

Memory read methods, apparatus, and systems

Non-volatile memory with both single and multiple level cells

Multiple select gates with non-volatile memory cells

Memory voltage cycle adjustment

Patents Applicationslast 30 patents

PROGRAM AND READ TRIM SETTING

PROGRAM AND READ TRIM SETTING

NON-VOLATILE MULTILEVEL MEMORY CELLS

NON-VOLATILE MEMORY WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS

MEMORY CELL OPERATION

NON-VOLATILE MULTILEVEL MEMORY CELLS

NAND WITH BACK BIASED OPERATION

NON-VOLATILE MEMORY WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS

MEMORY VOLTAGE CYCLE ADJUSTMENT

MULTIPLE SELECT GATES WITH NON-VOLATILE MEMORY CELLS

MEMORY CELL OPERATION

MEMORY CELL PROGRAMMING

SENSING MEMORY CELLS

NON-VOLATILE MEMORY CELL READ FAILURE REDUCTION

MULTIPLE SELECT GATES WITH NON-VOLATILE MEMORY CELLS

OPERATING MEMORY CELLS

NON-VOLATILE MEMORY WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS

NON-VOLATILE MULTILEVEL MEMORY CELLS

NAND WITH BACK BIASED OPERATION

MEMORY VOLTAGE CYCLE ADJUSTMENT

NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING

MULTILEVEL MEMORY CELL OPERATION

MEMORY CELL PROGRAMMING

NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING

NON-VOLATILE MEMORY CELL READ FAILURE REDUCTION

NAND WITH BACK BIASED OPERATION

MEMORY DEVICES HAVING REDUCED WORD LINE CURRENT AND METHOD OF OPERA...

Adjusting program and erase voltages in a memory device

METHOD, APPARATUS, AND SYSTEM FOR ERASING MEMORY

MEMORY READ METHODS, APPARATUS, AND SYSTEMS