Senani Gunaratna

Person

Campbell, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multiple mode device implementation for programmable logic devices
- Patent number 10,630,269
- Issue date Apr 21, 2020
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible ripple mode device implementation for programmable logic d...
- Patent number 10,382,021
- Issue date Aug 13, 2019
- LATTICE SEMICONDUCTOR CORPORATION
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple mode device implementation for programmable logic devices
- Patent number 10,141,917
- Issue date Nov 27, 2018
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective power gating of routing resource configuration memory bit...
- Patent number 10,079,054
- Issue date Sep 18, 2018
- LATTICE SEMICONDUCTOR CORPORATION
- Senani Gunaratna
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexible ripple mode device implementation for programmable logic d...
- Patent number 9,735,761
- Issue date Aug 15, 2017
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple mode device implementation for programmable logic devices
- Patent number 9,716,491
- Issue date Jul 25, 2017
- LATTICE SEMICONDUCTOR CORPORATION
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed complementary NMOS LUT logic
- Patent number 9,543,950
- Issue date Jan 10, 2017
- LATTICE SEMICONDUCTOR CORPORATION
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Shared logic for multiple registers with asynchronous initialization
- Patent number 9,252,755
- Issue date Feb 2, 2016
- LATTICE SEMICONDUCTOR CORPORATION
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adjustable interface buffer circuit between a programmable logic de...
- Patent number 8,487,652
- Issue date Jul 16, 2013
- QuickLogic Corporation
- Ket-Chong Yap
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adjustable interface buffer circuit between a programmable logic de...
- Patent number 8,018,248
- Issue date Sep 13, 2011
- QuickLogic Corporation
- Ket-Chong Yap
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic clock control
- Patent number 7,443,222
- Issue date Oct 28, 2008
- QuickLogic Corporation
- Timothy Saxe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serializer/deserializer embedded in a programmable device
- Patent number 6,542,096
- Issue date Apr 1, 2003
- QuickLogic Corporation
- Andrew K. Chan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Clock Insertion Delay Systems and Methods
- Publication number 20240183902
- Publication date Jun 6, 2024
- Lattice Semiconductor Corporation
- Maryam Shahbazi
- G01 - MEASURING TESTING
Information Patent Application
MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20190158073
- Publication date May 23, 2019
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20170324401
- Publication date Nov 9, 2017
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE RIPPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC D...
- Publication number 20170324400
- Publication date Nov 9, 2017
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE RIPPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC D...
- Publication number 20160028400
- Publication date Jan 28, 2016
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED LOGIC FOR MULTIPLE REGISTERS WITH ASYNCHRONOUS INITIALIZATION
- Publication number 20160028383
- Publication date Jan 28, 2016
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20160028401
- Publication date Jan 28, 2016
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH SPEED COMPLEMENTARY NMOS LUT LOGIC
- Publication number 20160020767
- Publication date Jan 21, 2016
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adjustable Interface Buffer Circuit Between A Programmable Logic De...
- Publication number 20110298492
- Publication date Dec 8, 2011
- QuickLogic Corporation
- Ket-Chong Yap
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW POWER PROGRAMMABLE LOGIC DEVICES
- Publication number 20110074464
- Publication date Mar 31, 2011
- Senani Gunaratna
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adjustable interface buffer circuit between a programmable logic de...
- Publication number 20080074141
- Publication date Mar 27, 2008
- QuickLogic Corporation
- Ket-Chong Yap
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SERIALIZER/DESERIALIZER EMBEDDED IN A PROGRAMMABLE DEVICE
- Publication number 20030039168
- Publication date Feb 27, 2003
- QuickLogic Corporation
- Andrew K. Chan
- G11 - INFORMATION STORAGE

Senani Gunaratna

Person

Patents Grantslast 30 patents

Multiple mode device implementation for programmable logic devices

Flexible ripple mode device implementation for programmable logic d...

Multiple mode device implementation for programmable logic devices

Selective power gating of routing resource configuration memory bit...

Flexible ripple mode device implementation for programmable logic d...

Multiple mode device implementation for programmable logic devices

High speed complementary NMOS LUT logic

Shared logic for multiple registers with asynchronous initialization

Adjustable interface buffer circuit between a programmable logic de...

Adjustable interface buffer circuit between a programmable logic de...

Dynamic clock control

Serializer/deserializer embedded in a programmable device

Patents Applicationslast 30 patents

Clock Insertion Delay Systems and Methods

MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES

MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES

FLEXIBLE RIPPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC D...

FLEXIBLE RIPPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC D...

SHARED LOGIC FOR MULTIPLE REGISTERS WITH ASYNCHRONOUS INITIALIZATION

MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES

HIGH SPEED COMPLEMENTARY NMOS LUT LOGIC

Adjustable Interface Buffer Circuit Between A Programmable Logic De...

LOW POWER PROGRAMMABLE LOGIC DEVICES

Adjustable interface buffer circuit between a programmable logic de...

SERIALIZER/DESERIALIZER EMBEDDED IN A PROGRAMMABLE DEVICE