Seng Guan Chow

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device and method to minimize stress on stack via
- Patent number 12,080,600
- Issue date Sep 3, 2024
- STATS ChipPAC Pte. Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming interposer frame over se...
- Patent number RE48408
- Issue date Jan 26, 2021
- JCET Semiconductor (Shaoxing) Co., Ltd.
- Reza A. Pagaila
Information Patent Grant
Semiconductor device and method to minimize stress on stack via
- Patent number 10,804,153
- Issue date Oct 13, 2020
- STATS ChipPAC Pte. Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming interposer frame over se...
- Patent number RE48111
- Issue date Jul 21, 2020
- JCET Semiconductor (Shaoxing) Co. Ltd.
- Reza A. Pagaila
Information Patent Grant
Semiconductor device and method of controlling warpage in reconstit...
- Patent number 10,297,556
- Issue date May 21, 2019
- STATS ChipPAC Pte. Ltd.
- Kian Meng Heng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of controlling warpage in reconstit...
- Patent number 10,163,747
- Issue date Dec 25, 2018
- STATS ChipPAC Pte. Ltd.
- Kian Meng Heng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming stress relief layer betw...
- Patent number 10,083,916
- Issue date Sep 25, 2018
- STATS ChipPAC Pte. Ltd.
- Il Kwon Shim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming interposer frame over se...
- Patent number 9,893,045
- Issue date Feb 13, 2018
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package using through-hole via die on saw streets
- Patent number 9,847,253
- Issue date Dec 19, 2017
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming insulating layer dispose...
- Patent number 9,666,500
- Issue date May 30, 2017
- STATS ChipPAC Pte. Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming EWLB semiconductor packa...
- Patent number 9,620,557
- Issue date Apr 11, 2017
- STATS ChipPAC Pte. Ltd.
- Seng Guan Chow
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Semiconductor device and method of controlling warpage in reconstit...
- Patent number 9,607,965
- Issue date Mar 28, 2017
- STATS ChipPAC Pte. Ltd.
- Kian Meng Heng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming interconnect structure f...
- Patent number 9,559,029
- Issue date Jan 31, 2017
- STATS ChipPAC Pte. Ltd.
- Il Kwon Shim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-in-package using through-hole via die on saw streets
- Patent number 9,524,938
- Issue date Dec 20, 2016
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming no-flow underfill materi...
- Patent number 9,524,955
- Issue date Dec 20, 2016
- STATS ChipPAC Pte. Ltd.
- Rui Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package and method of forming z-direction conductive...
- Patent number 9,515,016
- Issue date Dec 6, 2016
- STATS ChipPAC Pte. Ltd.
- Rui Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming compliant stress relief...
- Patent number 9,508,621
- Issue date Nov 29, 2016
- STATS ChipPAC Pte. Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with patterned substrate and me...
- Patent number 9,299,648
- Issue date Mar 29, 2016
- Stats Chippac Ltd.
- Il Kwon Shim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package system with cavity substrate and manufacturin...
- Patent number 9,293,350
- Issue date Mar 22, 2016
- Stats Chippac Ltd.
- Seng Guan Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming semiconductor package us...
- Patent number 9,275,877
- Issue date Mar 1, 2016
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming an IPD beneath a semicon...
- Patent number 9,257,356
- Issue date Feb 9, 2016
- STATS ChipPAC, Ltd.
- Rui Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming EWLB semiconductor packa...
- Patent number 9,252,172
- Issue date Feb 2, 2016
- STATS ChipPAC, Ltd.
- Seng Guan Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming interconnect structure f...
- Patent number 9,252,066
- Issue date Feb 2, 2016
- STATS ChipPAC, Ltd.
- Il Kwon Shim
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor device and method of forming interposer frame over se...
- Patent number 9,240,380
- Issue date Jan 19, 2016
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor package system with cut multiple lead pads
- Patent number 9,202,777
- Issue date Dec 1, 2015
- Stats Chippac Ltd.
- Lionel Chien Hui Tay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package system with locking terminal
- Patent number 9,177,898
- Issue date Nov 3, 2015
- Stats Chippac Ltd.
- Il Kwon Shim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming openings through encapsu...
- Patent number 9,171,769
- Issue date Oct 27, 2015
- STATS ChipPAC, Ltd.
- Seng Guan Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with package underfill and meth...
- Patent number 9,123,733
- Issue date Sep 1, 2015
- Stats Chippac Ltd.
- Rui Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming conductive posts embedde...
- Patent number 9,099,455
- Issue date Aug 4, 2015
- STATS ChipPAC, Ltd.
- Seng Guan Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming insulating layer dispose...
- Patent number 9,087,930
- Issue date Jul 21, 2015
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor Device and Method to Minimize Stress on Stack Via
- Publication number 20200402855
- Publication date Dec 24, 2020
- STATS ChipPAC Pte Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Controlling Warpage in Reconstit...
- Publication number 20170194228
- Publication date Jul 6, 2017
- STATS ChipPAC Pte Ltd.
- Kian Meng Heng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Controlling Warpage in Reconstit...
- Publication number 20170133330
- Publication date May 11, 2017
- STATS ChipPAC Pte Ltd.
- Kian Meng Heng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method to Minimize Stress on Stack Via
- Publication number 20160276237
- Publication date Sep 22, 2016
- STATS ChipPAC Pte Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Interposer Frame Over Se...
- Publication number 20160111410
- Publication date Apr 21, 2016
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming EWLB Semiconductor Packa...
- Publication number 20160104731
- Publication date Apr 14, 2016
- STATS ChipPAC, Ltd.
- Seng Guan Chow
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Semiconductor Device and Method of Forming Insulating Layer Dispose...
- Publication number 20150228552
- Publication date Aug 13, 2015
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Stress Relief Layer Betw...
- Publication number 20150179587
- Publication date Jun 25, 2015
- STATS ChipPAC, Ltd.
- Il Kwon Shim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Compliant Stress Relief...
- Publication number 20150145126
- Publication date May 28, 2015
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Controlling Warpage in Reconstit...
- Publication number 20150084213
- Publication date Mar 26, 2015
- STATS ChipPAC, Ltd.
- Kian Meng Heng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Interconnect Structure f...
- Publication number 20150061124
- Publication date Mar 5, 2015
- STATS ChipPAC, Ltd.
- Il Kwon Shim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING STRUCTURE
- Publication number 20140335655
- Publication date Nov 13, 2014
- Rui Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Interposer Frame Over Se...
- Publication number 20140327145
- Publication date Nov 6, 2014
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Insulating Layer Dispose...
- Publication number 20140246779
- Publication date Sep 4, 2014
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Embedded Semiconductor Die Package and Method of Making the Same Us...
- Publication number 20140127858
- Publication date May 8, 2014
- STATS ChipPAC, Ltd.
- Il Kwon Shim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Package-in-Package Using Through-Hole Via Die on Saw Streets
- Publication number 20130214385
- Publication date Aug 22, 2013
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Insulating Layer Dispose...
- Publication number 20130175696
- Publication date Jul 11, 2013
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSE...
- Publication number 20130113092
- Publication date May 9, 2013
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Interposer Frame Over Se...
- Publication number 20130105989
- Publication date May 2, 2013
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Package and Method of Forming Z-Direction Conductive...
- Publication number 20130075899
- Publication date Mar 28, 2013
- STATS ChipPAC, Ltd.
- Rui Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Different Height Conduct...
- Publication number 20130075903
- Publication date Mar 28, 2013
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Conductive Posts Embedde...
- Publication number 20130075902
- Publication date Mar 28, 2013
- STATS ChipPAC, Ltd.
- Seng Guan Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Semiconductor Package Us...
- Publication number 20130069241
- Publication date Mar 21, 2013
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming EWLB Semiconductor Packa...
- Publication number 20120306038
- Publication date Dec 6, 2012
- STATS ChipPAC, Ltd.
- Seng Guan Chow
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERNAL STACKING MODULE
- Publication number 20120292750
- Publication date Nov 22, 2012
- Seng Guan Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Interconnect Structure f...
- Publication number 20120286422
- Publication date Nov 15, 2012
- STATS ChipPAC, Ltd.
- II Kwon Shim
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Semiconductor Device and Method of Forming Stress Relief Layer Betw...
- Publication number 20120223426
- Publication date Sep 6, 2012
- STATS ChipPAC, Ltd.
- Il Kwon Shim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming the Device Using Sacrifi...
- Publication number 20120217634
- Publication date Aug 30, 2012
- STATS ChipPAC, Ltd.
- Il Kwon Shim
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Semiconductor Device and Method of Forming Interconnect Structure f...
- Publication number 20120217647
- Publication date Aug 30, 2012
- STATS ChipPAC, Ltd.
- Il Kwon Shim
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH MOLDED CAVITY
- Publication number 20120217659
- Publication date Aug 30, 2012
- Seng Guan Chow
- H01 - BASIC ELECTRIC ELEMENTS

Seng Guan Chow

Person

Patents Grantslast 30 patents

Semiconductor device and method to minimize stress on stack via

Semiconductor device and method of forming interposer frame over se...

Semiconductor device and method to minimize stress on stack via

Semiconductor device and method of forming interposer frame over se...

Semiconductor device and method of controlling warpage in reconstit...

Semiconductor device and method of controlling warpage in reconstit...

Semiconductor device and method of forming stress relief layer betw...

Semiconductor device and method of forming interposer frame over se...

Package-on-package using through-hole via die on saw streets

Semiconductor device and method of forming insulating layer dispose...

Semiconductor device and method of forming EWLB semiconductor packa...

Semiconductor device and method of controlling warpage in reconstit...

Semiconductor device and method of forming interconnect structure f...

Package-in-package using through-hole via die on saw streets

Semiconductor device and method of forming no-flow underfill materi...

Semiconductor package and method of forming z-direction conductive...

Semiconductor device and method of forming compliant stress relief...

Integrated circuit packaging system with patterned substrate and me...

Semiconductor package system with cavity substrate and manufacturin...

Semiconductor device and method of forming semiconductor package us...

Semiconductor device and method of forming an IPD beneath a semicon...

Semiconductor device and method of forming EWLB semiconductor packa...

Semiconductor device and method of forming interconnect structure f...

Semiconductor device and method of forming interposer frame over se...

Semiconductor package system with cut multiple lead pads

Integrated circuit package system with locking terminal

Semiconductor device and method of forming openings through encapsu...

Integrated circuit packaging system with package underfill and meth...

Semiconductor device and method of forming conductive posts embedde...

Semiconductor device and method of forming insulating layer dispose...

Patents Applicationslast 30 patents

Semiconductor Device and Method to Minimize Stress on Stack Via

Semiconductor Device and Method of Controlling Warpage in Reconstit...

Semiconductor Device and Method of Controlling Warpage in Reconstit...

Semiconductor Device and Method to Minimize Stress on Stack Via

Semiconductor Device and Method of Forming Interposer Frame Over Se...

Semiconductor Device and Method of Forming EWLB Semiconductor Packa...

Semiconductor Device and Method of Forming Insulating Layer Dispose...

Semiconductor Device and Method of Forming Stress Relief Layer Betw...

Semiconductor Device and Method of Forming Compliant Stress Relief...

Semiconductor Device and Method of Controlling Warpage in Reconstit...

Semiconductor Device and Method of Forming Interconnect Structure f...

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING STRUCTURE

Semiconductor Device and Method of Forming Interposer Frame Over Se...

Semiconductor Device and Method of Forming Insulating Layer Dispose...

Embedded Semiconductor Die Package and Method of Making the Same Us...

Package-in-Package Using Through-Hole Via Die on Saw Streets

Semiconductor Device and Method of Forming Insulating Layer Dispose...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSE...

Semiconductor Device and Method of Forming Interposer Frame Over Se...

Semiconductor Package and Method of Forming Z-Direction Conductive...

Semiconductor Device and Method of Forming Different Height Conduct...

Semiconductor Device and Method of Forming Conductive Posts Embedde...

Semiconductor Device and Method of Forming Semiconductor Package Us...

Semiconductor Device and Method of Forming EWLB Semiconductor Packa...

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERNAL STACKING MODULE

Semiconductor Device and Method of Forming Interconnect Structure f...

Semiconductor Device and Method of Forming Stress Relief Layer Betw...

Semiconductor Device and Method of Forming the Device Using Sacrifi...

Semiconductor Device and Method of Forming Interconnect Structure f...

INTEGRATED CIRCUIT PACKAGE WITH MOLDED CAVITY