Serafino Bueti

Person

Waterbury, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Structure for hardware assisted bus state transition circuit using...
- Patent number 8,347,019
- Issue date Jan 1, 2013
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip identification circuit incorporating pairs of conductors, e...
- Patent number 8,291,357
- Issue date Oct 16, 2012
- International Business Machines Corporation
- Serafino Bueti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simulation of digital circuits
- Patent number 8,234,104
- Issue date Jul 31, 2012
- International Business Machines Corporation
- John Joseph Bergkvist, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic critical path detector for digital logic circuit paths
- Patent number 8,132,136
- Issue date Mar 6, 2012
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and systems of powering on integrated circuit
- Patent number 8,016,482
- Issue date Sep 13, 2011
- International Business Machines Corporation
- Igor Arsovski
- G05 - CONTROLLING REGULATING
Information Patent Grant
Dynamic critical path detector for digital logic circuit paths
- Patent number 7,941,772
- Issue date May 10, 2011
- International Business Machines Corporation
- Serafino Bueti
- G01 - MEASURING TESTING
Information Patent Grant
System and method for system-on-chip interconnect verification
- Patent number 7,865,789
- Issue date Jan 4, 2011
- International Business Machines Corporation
- Serafino Bueti
- G01 - MEASURING TESTING
Information Patent Grant
Structure for task based debugger (transaction-event-job-trigger)
- Patent number 7,823,017
- Issue date Oct 26, 2010
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transition balancing for noise reduction/Di/Dt reduction during des...
- Patent number 7,823,107
- Issue date Oct 26, 2010
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design structures of powering on integrated circuit
- Patent number 7,716,007
- Issue date May 11, 2010
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transition balancing for noise reduction /Di/Dt reduction during de...
- Patent number 7,643,591
- Issue date Jan 5, 2010
- International Business Machines Corproation
- Igor Arsovski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Task based debugger (transaction-event-job-trigger)
- Patent number 7,594,140
- Issue date Sep 22, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of manufacturing integrated circuits using pre-made and pre-...
- Patent number 7,519,941
- Issue date Apr 14, 2009
- International Business Machines Corporation
- Serafino Bueti
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Clock distribution network, structure, and method for providing bal...
- Patent number 7,511,548
- Issue date Mar 31, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design structures, method and systems of powering on integrated cir...
- Patent number 7,483,806
- Issue date Jan 27, 2009
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock distribution network, structure, and method for providing bal...
- Patent number 7,479,819
- Issue date Jan 20, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for system-on-chip interconnect verification
- Patent number 7,313,738
- Issue date Dec 25, 2007
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for implementing an integrated circuit IP core...
- Patent number 7,308,668
- Issue date Dec 11, 2007
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for monitoring integrated circuit temperature...
- Patent number 7,275,011
- Issue date Sep 25, 2007
- International Business Machines Corporation
- Serafino Bueti
- G01 - MEASURING TESTING
Information Patent Grant
Communication systems and methods using microelectronics power dist...
- Patent number 7,129,821
- Issue date Oct 31, 2006
- International Business Machines Corporation
- Serafino Bueti
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
SIMULATION OF DIGITAL CIRCUITS
- Publication number 20090265154
- Publication date Oct 22, 2009
- John Joseph Bergkvist, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN IN...
- Publication number 20090132732
- Publication date May 21, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE FOR UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRON...
- Publication number 20090132747
- Publication date May 21, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transition Balancing For Noise Reduction/Di/Dt Reduction During Des...
- Publication number 20090106724
- Publication date Apr 23, 2009
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN STRUCTURE FOR CHIP IDENTIFICATION SYSTEM
- Publication number 20090094566
- Publication date Apr 9, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHIP IDENTIFICATION SYSTEM AND METHOD
- Publication number 20090091351
- Publication date Apr 9, 2009
- Serafino Bueti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS
- Publication number 20090044160
- Publication date Feb 12, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS
- Publication number 20090044054
- Publication date Feb 12, 2009
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURES OF POWERING ON INTEGRATED CIRCUIT
- Publication number 20090024972
- Publication date Jan 22, 2009
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT
- Publication number 20090022203
- Publication date Jan 22, 2009
- Igor Arsovski
- G05 - CONTROLLING REGULATING
Information Patent Application
DESIGN STRUCTURES, METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIR...
- Publication number 20090021085
- Publication date Jan 22, 2009
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN STRUCTURE FOR HARDWARE ASSISTED BUS STATE TRANSITION CIRCUIT...
- Publication number 20080282015
- Publication date Nov 13, 2008
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design Structure for a Clock Distribution Network, Structure, and M...
- Publication number 20080229266
- Publication date Sep 18, 2008
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design Structure for a Clock Distribution Network, Structure, and M...
- Publication number 20080229265
- Publication date Sep 18, 2008
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN STRUCTURE FOR TASK BASED DEBUGGER (TRANSACTION-EVENT -JOB-TR...
- Publication number 20080215923
- Publication date Sep 4, 2008
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for system-on-chip interconnect verification
- Publication number 20080215945
- Publication date Sep 4, 2008
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ASSISTED BUS STATE TRANSITION USING CONTENT ADDRESSABLE ME...
- Publication number 20080183941
- Publication date Jul 31, 2008
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Distribution Network, Structure, And Method For Providing Bal...
- Publication number 20080143416
- Publication date Jun 19, 2008
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Distribution Network, Structure, And Method For Providing Bal...
- Publication number 20080148204
- Publication date Jun 19, 2008
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TASK BASED DEBUGGER (TRANSACATION-EVENT-JOB-TRIGGER)
- Publication number 20080127216
- Publication date May 29, 2008
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSITION BALANCING FOR NOISE REDUCTION /di/dt REDUCTION DURING DE...
- Publication number 20080043890
- Publication date Feb 21, 2008
- Igor Arsovski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD OF MANUFACTURING INTEGRATED CIRCUITS USING PRE-MADE AND PRE-...
- Publication number 20070245290
- Publication date Oct 18, 2007
- Serafino Bueti
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING AN INTEGRATED CIRCUIT IP CORE...
- Publication number 20070006108
- Publication date Jan 4, 2007
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR MONITORING INTEGRATED CIRCUIT TEMPERATURE...
- Publication number 20070005290
- Publication date Jan 4, 2007
- International Business Machines Corporation
- Serafino Bueti
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION
- Publication number 20060242524
- Publication date Oct 26, 2006
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR ARBITRATION BETWEEN SHARED PERIPHERAL CORE DE...
- Publication number 20060041705
- Publication date Feb 23, 2006
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMUNICATION SYSTEMS AND METHODS USING MICROELECTRONICS POWER DIST...
- Publication number 20060038444
- Publication date Feb 23, 2006
- International Business Machines Corporation
- Serafino Bueti
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND APPARATUS FOR DYNAMICALLY MANAGING POWER CONSUMPTIONS OF...
- Publication number 20050265462
- Publication date Dec 1, 2005
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING

Serafino Bueti

Person

Patents Grantslast 30 patents

Structure for hardware assisted bus state transition circuit using...

On-chip identification circuit incorporating pairs of conductors, e...

Simulation of digital circuits

Dynamic critical path detector for digital logic circuit paths

Method and systems of powering on integrated circuit

Dynamic critical path detector for digital logic circuit paths

System and method for system-on-chip interconnect verification

Structure for task based debugger (transaction-event-job-trigger)

Transition balancing for noise reduction/Di/Dt reduction during des...

Design structures of powering on integrated circuit

Transition balancing for noise reduction /Di/Dt reduction during de...

Task based debugger (transaction-event-job-trigger)

Method of manufacturing integrated circuits using pre-made and pre-...

Clock distribution network, structure, and method for providing bal...

Design structures, method and systems of powering on integrated cir...

Clock distribution network, structure, and method for providing bal...

System and method for system-on-chip interconnect verification

Apparatus and method for implementing an integrated circuit IP core...

Method and apparatus for monitoring integrated circuit temperature...

Communication systems and methods using microelectronics power dist...

Patents Applicationslast 30 patents

SIMULATION OF DIGITAL CIRCUITS

UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN IN...

STRUCTURE FOR UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRON...

Transition Balancing For Noise Reduction/Di/Dt Reduction During Des...

DESIGN STRUCTURE FOR CHIP IDENTIFICATION SYSTEM

CHIP IDENTIFICATION SYSTEM AND METHOD

DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS

DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS

STRUCTURES OF POWERING ON INTEGRATED CIRCUIT

METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT

DESIGN STRUCTURES, METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIR...

DESIGN STRUCTURE FOR HARDWARE ASSISTED BUS STATE TRANSITION CIRCUIT...

Design Structure for a Clock Distribution Network, Structure, and M...

Design Structure for a Clock Distribution Network, Structure, and M...

DESIGN STRUCTURE FOR TASK BASED DEBUGGER (TRANSACTION-EVENT -JOB-TR...

System and method for system-on-chip interconnect verification

HARDWARE ASSISTED BUS STATE TRANSITION USING CONTENT ADDRESSABLE ME...

Clock Distribution Network, Structure, And Method For Providing Bal...

Clock Distribution Network, Structure, And Method For Providing Bal...

TASK BASED DEBUGGER (TRANSACATION-EVENT-JOB-TRIGGER)

TRANSITION BALANCING FOR NOISE REDUCTION /di/dt REDUCTION DURING DE...

METHOD OF MANUFACTURING INTEGRATED CIRCUITS USING PRE-MADE AND PRE-...

APPARATUS AND METHOD FOR IMPLEMENTING AN INTEGRATED CIRCUIT IP CORE...

METHOD AND APPARATUS FOR MONITORING INTEGRATED CIRCUIT TEMPERATURE...

SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION

SYSTEM AND METHOD FOR ARBITRATION BETWEEN SHARED PERIPHERAL CORE DE...

COMMUNICATION SYSTEMS AND METHODS USING MICROELECTRONICS POWER DIST...

METHOD AND APPARATUS FOR DYNAMICALLY MANAGING POWER CONSUMPTIONS OF...