Sergei V. Koveshnikov

Person

Vancouver, WA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated structures containing vertically-stacked memory cells
- Patent number 11,309,321
- Issue date Apr 19, 2022
- Micron Technology, Inc.
- Haitao Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Building stacked hollow channels for a three dimensional circuit de...
- Patent number 11,018,149
- Issue date May 25, 2021
- Intel Corporation
- Zhenyu Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated structures containing vertically-stacked memory cells
- Patent number 10,892,268
- Issue date Jan 12, 2021
- Micron Technology, Inc.
- Haitao Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated structures containing vertically-stacked memory cells
- Patent number 10,381,365
- Issue date Aug 13, 2019
- Micron Technology, Inc.
- Haitao Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated structures containing vertically-stacked memory cells
- Patent number 9,761,599
- Issue date Sep 12, 2017
- Micron Technology, Inc.
- Haitao Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of determining nitrogen concentration within a wafer
- Patent number 6,896,727
- Issue date May 24, 2005
- SEH America, Inc.
- Sergei V. Koveshnikov
- G01 - MEASURING TESTING
Information Patent Grant
Method of producing an SOI wafer
- Patent number 6,794,227
- Issue date Sep 21, 2004
- SEH America, Inc.
- Sergei V. Koveshnikov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High resistivity silicon wafer having electrically inactive dopant...
- Patent number 6,673,147
- Issue date Jan 6, 2004
- SEH America, Inc.
- Oleg V. Kononchuk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of producing a high resistivity silicon wafer utilizing heat...
- Patent number 6,669,777
- Issue date Dec 30, 2003
- SEH America, Inc.
- Oleg V. Kononchuk
- C30 - CRYSTAL GROWTH
Information Patent Grant
High resistivity silicon wafer produced by a controlled pull rate c...
- Patent number 6,669,775
- Issue date Dec 30, 2003
- SEH America, Inc.
- Oleg V. Kononchuk
- C30 - CRYSTAL GROWTH
Information Patent Grant
Method for evaluating impurity concentrations in epitaxial susceptors
- Patent number 6,649,427
- Issue date Nov 18, 2003
- SEH America, Inc.
- Sergei V. Koveshnikov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for evaluating impurity concentrations in epitaxial reagent...
- Patent number 6,632,688
- Issue date Oct 14, 2003
- SEH America, Inc.
- Sergei V. Koveshnikov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for evaluating impurity concentrations in unpolished wafers...
- Patent number 6,630,363
- Issue date Oct 7, 2003
- SEH America, Inc.
- Sergei V. Koveshnikov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for evaluating impurity concentrations in semiconductor subs...
- Patent number 6,620,632
- Issue date Sep 16, 2003
- SEH America, Inc.
- Sergei V. Koveshnikov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High resistivity silicon wafer with thick epitaxial layer and metho...
- Patent number 6,583,024
- Issue date Jun 24, 2003
- SEH America, Inc.
- Oleg V. Kononchuk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double side polished wafers having external gettering sites, and me...
- Patent number 6,576,501
- Issue date Jun 10, 2003
- SEH America, Inc.
- David A. Beauchaine
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High resistivity silicon wafer and method of producing same using t...
- Patent number 6,565,652
- Issue date May 20, 2003
- SEH America, Inc.
- Oleg V. Kononchuk
- C30 - CRYSTAL GROWTH
Information Patent Grant
Method for evaluating impurity concentrations in heat treatment fur...
- Patent number 6,423,556
- Issue date Jul 23, 2002
- SEH America, Inc.
- Sergei V. Koveshnikov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low cost silicon substrate with impurity gettering and latch up pro...
- Patent number 6,346,460
- Issue date Feb 12, 2002
- SEH America
- Oleg V. Kononchuk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming semiconductive active area having a proximity get...
- Patent number 6,339,011
- Issue date Jan 15, 2002
- Micron Technology, Inc.
- Fernando Gonzalez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Schottky metal detection method
- Patent number 5,943,552
- Issue date Aug 24, 1999
- SEH America, Inc.
- Sergei Viktor Koveshnikov
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Integrated Structures Containing Vertically-Stacked Memory Cells
- Publication number 20210082937
- Publication date Mar 18, 2021
- Micron Technology, Inc.
- Haitao Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Structures Containing Vertically-Stacked Memory Cells
- Publication number 20190312047
- Publication date Oct 10, 2019
- Micron Technology, Inc.
- Haitao Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Structures Containing Vertically-Stacked Memory Cells
- Publication number 20170373081
- Publication date Dec 28, 2017
- Micron Technology, Inc.
- Haitao Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Structures Containing Vertically-Stacked Memory Cells
- Publication number 20170053986
- Publication date Feb 23, 2017
- Micron Technology, Inc.
- Haitao Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BUILDING STACKED HOLLOW CHANNELS FOR A THREE DIMENSIONAL CIRCUIT DE...
- Publication number 20150279855
- Publication date Oct 1, 2015
- Intel Corporation
- Zhenyu Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Systems, methods and computer program products for determining cont...
- Publication number 20040010394
- Publication date Jan 15, 2004
- SEH America, Inc.
- Sergei V. Koveshnikov
- G01 - MEASURING TESTING
Information Patent Application
Method of producing an SOI wafer
- Publication number 20040002200
- Publication date Jan 1, 2004
- Sergei V. Koveshnikov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of determining nitrogen concentration within a wafer
- Publication number 20040000267
- Publication date Jan 1, 2004
- SHE America, Inc.
- Sergei V. Koveshnikov
- C30 - CRYSTAL GROWTH
Information Patent Application
Double side polished wafers having external gettering sites, and me...
- Publication number 20030224603
- Publication date Dec 4, 2003
- David A. Beauchaine
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Double side polished wafers having external gettering sites, and me...
- Publication number 20030224135
- Publication date Dec 4, 2003
- David A. Beauchaine
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR EVALUATING IMPURITY CONCENTRATIONS IN SEMICONDUCTOR SUBS...
- Publication number 20030138979
- Publication date Jul 24, 2003
- Sergei V. Koveshnikov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High resistivity silicon wafer having electrically inactive dopant...
- Publication number 20030106482
- Publication date Jun 12, 2003
- SEH America, Inc.
- Oleg V. Kononchuk
- C30 - CRYSTAL GROWTH
Information Patent Application
HIGH RESISTIVITY SILICON WAFER WITH THICK EPITAXIAL LAYER AND METHO...
- Publication number 20030109115
- Publication date Jun 12, 2003
- SEH Amercia, Inc.
- Oleg V. Kononchuk
- C30 - CRYSTAL GROWTH
Information Patent Application
HIGH RESISTIVITY SILICON WAFER AND METHOD OF PRODUCING SAME USING T...
- Publication number 20030106485
- Publication date Jun 12, 2003
- SEH America, Inc.
- Oleg V. Kononchuk
- C30 - CRYSTAL GROWTH
Information Patent Application
Method of producing a high resistivity silicon wafer utilizing heat...
- Publication number 20030106486
- Publication date Jun 12, 2003
- SEH America, Inc.
- Oleg V. Kononchuk
- C30 - CRYSTAL GROWTH
Information Patent Application
High resistivity silicon wafer produced by a controlled pull rate c...
- Publication number 20030106481
- Publication date Jun 12, 2003
- SEH America, Inc.
- Oleg V. Kononchuk
- C30 - CRYSTAL GROWTH
Information Patent Application
Method for evaluating impurity concentrations in unpolished wafers...
- Publication number 20020098601
- Publication date Jul 25, 2002
- Sergei V. Koveshnikov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for evaluating impurity concentrations in epitaxial reagent...
- Publication number 20020076839
- Publication date Jun 20, 2002
- Sergei V. Koveshnikov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for evaluating impurity concentrations in epitaxial susceptors
- Publication number 20020052095
- Publication date May 2, 2002
- Sergei V. Koveshnikov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for evaluating impurity concentrations in heat treatment fur...
- Publication number 20020048908
- Publication date Apr 25, 2002
- Sergei V. Koveshnikov
- H01 - BASIC ELECTRIC ELEMENTS

Sergei V. Koveshnikov

Person

Patents Grantslast 30 patents

Integrated structures containing vertically-stacked memory cells

Building stacked hollow channels for a three dimensional circuit de...

Integrated structures containing vertically-stacked memory cells

Integrated structures containing vertically-stacked memory cells

Integrated structures containing vertically-stacked memory cells

Method of determining nitrogen concentration within a wafer

Method of producing an SOI wafer

High resistivity silicon wafer having electrically inactive dopant...

Method of producing a high resistivity silicon wafer utilizing heat...

High resistivity silicon wafer produced by a controlled pull rate c...

Method for evaluating impurity concentrations in epitaxial susceptors

Method for evaluating impurity concentrations in epitaxial reagent...

Method for evaluating impurity concentrations in unpolished wafers...

Method for evaluating impurity concentrations in semiconductor subs...

High resistivity silicon wafer with thick epitaxial layer and metho...

Double side polished wafers having external gettering sites, and me...

High resistivity silicon wafer and method of producing same using t...

Method for evaluating impurity concentrations in heat treatment fur...

Low cost silicon substrate with impurity gettering and latch up pro...

Method of forming semiconductive active area having a proximity get...

Schottky metal detection method

Patents Applicationslast 30 patents

Integrated Structures Containing Vertically-Stacked Memory Cells

Integrated Structures Containing Vertically-Stacked Memory Cells

Integrated Structures Containing Vertically-Stacked Memory Cells

Integrated Structures Containing Vertically-Stacked Memory Cells

BUILDING STACKED HOLLOW CHANNELS FOR A THREE DIMENSIONAL CIRCUIT DE...

Systems, methods and computer program products for determining cont...

Method of producing an SOI wafer

Method of determining nitrogen concentration within a wafer

Double side polished wafers having external gettering sites, and me...

Double side polished wafers having external gettering sites, and me...

METHOD FOR EVALUATING IMPURITY CONCENTRATIONS IN SEMICONDUCTOR SUBS...

High resistivity silicon wafer having electrically inactive dopant...

HIGH RESISTIVITY SILICON WAFER WITH THICK EPITAXIAL LAYER AND METHO...

HIGH RESISTIVITY SILICON WAFER AND METHOD OF PRODUCING SAME USING T...

Method of producing a high resistivity silicon wafer utilizing heat...

High resistivity silicon wafer produced by a controlled pull rate c...

Method for evaluating impurity concentrations in unpolished wafers...

Method for evaluating impurity concentrations in epitaxial reagent...

Method for evaluating impurity concentrations in epitaxial susceptors

Method for evaluating impurity concentrations in heat treatment fur...