SERGIO A. AJURIA

Person

AUSTIN, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor manufacturing using disposable test circuitry within...
- Patent number 10,553,508
- Issue date Feb 4, 2020
- NXP USA, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with embedded capacitor and methods of manufa...
- Patent number 10,522,615
- Issue date Dec 31, 2019
- NXP USA, INC.
- Sergio A. Ajuria
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor manufacturing for forming bond pads and seal rings
- Patent number 9,601,354
- Issue date Mar 21, 2017
- NXP USA, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with embedded capacitor and methods of manufa...
- Patent number 9,548,266
- Issue date Jan 17, 2017
- NXP USA, INC.
- Sergio A. Ajuria
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a packaged semiconductor device
- Patent number 9,134,366
- Issue date Sep 15, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Sergio A. Ajuria
- G01 - MEASURING TESTING
Information Patent Grant
Package level ESD protection and method therefor
- Patent number 8,059,380
- Issue date Nov 15, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Sergio A. Ajuria
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Combined trench isolation and inlaid process for integrated circuit...
- Patent number 5,963,818
- Issue date Oct 5, 1999
- Motorola, Inc.
- Soolin Kao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a semiconductor device having a nitrided oxide d...
- Patent number 5,885,870
- Issue date Mar 23, 1999
- Motorola, Inc.
- Bikas Maiti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon chemical mechanical polish etch (CMP) stop for reduced tren...
- Patent number 5,837,612
- Issue date Nov 17, 1998
- Motorola, Inc.
- Sergio Ajuria
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a fully self-aligned soi mosfet
- Patent number 5,736,435
- Issue date Apr 7, 1998
- Motorola, Inc.
- Suresh Venkatesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming concurrent top oxides using reoxidized silicon i...
- Patent number 5,665,620
- Issue date Sep 9, 1997
- Motorola, Inc.
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure having an air region and method of forming...
- Patent number 5,510,645
- Issue date Apr 23, 1996
- Motorola, Inc.
- Jon T. Fitch
- G01 - MEASURING TESTING
Information Patent Grant
Method of forming a semiconductor structure having an air region
- Patent number 5,324,683
- Issue date Jun 28, 1994
- Motorola, Inc.
- Jon T. Fitch
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR PACKAGE WITH EMBEDDED CAPACITOR AND METHODS OF MANUFA...
- Publication number 20170084682
- Publication date Mar 23, 2017
- NXP USA, Inc.
- SERGIO A. AJURIA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH EMBEDDED CAPACITOR AND METHODS OF MANUFA...
- Publication number 20160064324
- Publication date Mar 3, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Sergio A. Ajuria
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR MANUFACTURING FOR FORMING BOND PADS AND SEAL RINGS
- Publication number 20160064294
- Publication date Mar 3, 2016
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Manufacturing Using Disposable Test Circuitry Within...
- Publication number 20150200146
- Publication date Jul 16, 2015
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A PACKAGED SEMICONDUCTOR DEVICE
- Publication number 20150061709
- Publication date Mar 5, 2015
- Sergio A. Ajuria
- G01 - MEASURING TESTING
Information Patent Application
PACKAGE LEVEL ESD PROTECTION AND METHOD THEREFOR
- Publication number 20090284881
- Publication date Nov 19, 2009
- Sergio A. Ajuria
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Probe pad arrangement for an integrated circuit and method of forming
- Publication number 20060022353
- Publication date Feb 2, 2006
- Sergio A. Ajuria
- H01 - BASIC ELECTRIC ELEMENTS

SERGIO A. AJURIA

Person

Patents Grantslast 30 patents

Semiconductor manufacturing using disposable test circuitry within...

Semiconductor package with embedded capacitor and methods of manufa...

Semiconductor manufacturing for forming bond pads and seal rings

Semiconductor package with embedded capacitor and methods of manufa...

Method for forming a packaged semiconductor device

Package level ESD protection and method therefor

Combined trench isolation and inlaid process for integrated circuit...

Method for forming a semiconductor device having a nitrided oxide d...

Silicon chemical mechanical polish etch (CMP) stop for reduced tren...

Process for fabricating a fully self-aligned soi mosfet

Method for forming concurrent top oxides using reoxidized silicon i...

Semiconductor structure having an air region and method of forming...

Method of forming a semiconductor structure having an air region

Patents Applicationslast 30 patents

SEMICONDUCTOR PACKAGE WITH EMBEDDED CAPACITOR AND METHODS OF MANUFA...

SEMICONDUCTOR PACKAGE WITH EMBEDDED CAPACITOR AND METHODS OF MANUFA...

SEMICONDUCTOR MANUFACTURING FOR FORMING BOND PADS AND SEAL RINGS

Semiconductor Manufacturing Using Disposable Test Circuitry Within...

METHOD FOR FORMING A PACKAGED SEMICONDUCTOR DEVICE

PACKAGE LEVEL ESD PROTECTION AND METHOD THEREFOR

Probe pad arrangement for an integrated circuit and method of forming