Seshu V. SATTIRAJU

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
3D interconnect structure comprising through-silicon vias combined...
- Patent number 9,530,740
- Issue date Dec 27, 2016
- Intel Corporation
- Kevin J. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D interconnect structure comprising fine pitch single damascene ba...
- Patent number 9,449,913
- Issue date Sep 20, 2016
- Intel Corporation
- Kevin J. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D interconnect structure comprising through-silicon vias combined...
- Patent number 9,142,510
- Issue date Sep 22, 2015
- Intel Corporation
- Kevin J. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Under bump metallization layer to enable use of high tin content so...
- Patent number 7,064,446
- Issue date Jun 20, 2006
- Intel Corporation
- John P. Barnak
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
BARRIER MATERIALS BETWEEN BUMPS AND PADS
- Publication number 20210057348
- Publication date Feb 25, 2021
- Intel Corporation
- Ehren HWANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP ASSEMBLIES EMPLOYING SOLDER BONDS TO BACK-SIDE LANDS INCLUDING...
- Publication number 20190237391
- Publication date Aug 1, 2019
- Intel Corporation
- Seshu V. SATTIRAJU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D INTERCONNECT STRUCTURE COMPRISING THROUGH-SILICON VIAS COMBINED...
- Publication number 20150364425
- Publication date Dec 17, 2015
- Intel Corporation
- Kevin J. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D INTERCONNECT STRUCTURE COMPRISING THROUGH-SILICON VIAS COMBINED...
- Publication number 20130285257
- Publication date Oct 31, 2013
- Kevin J. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D INTERCONNECT STRUCTURE COMPRISING FINE PITCH SINGLE DAMASCENE BA...
- Publication number 20130256910
- Publication date Oct 3, 2013
- Kevin J. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Under bump metallization layer to enable use of high tin content so...
- Publication number 20050250323
- Publication date Nov 10, 2005
- John P. Barnak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UNDER BUMP METALLIZATION LAYER TO ENABLE USE OF HIGH TIN CONTENT SO...
- Publication number 20050212133
- Publication date Sep 29, 2005
- John P. Barnak
- H01 - BASIC ELECTRIC ELEMENTS

Seshu V. SATTIRAJU

Person

Patents Grantslast 30 patents

3D interconnect structure comprising through-silicon vias combined...

3D interconnect structure comprising fine pitch single damascene ba...

3D interconnect structure comprising through-silicon vias combined...

Under bump metallization layer to enable use of high tin content so...

Patents Applicationslast 30 patents

BARRIER MATERIALS BETWEEN BUMPS AND PADS

CHIP ASSEMBLIES EMPLOYING SOLDER BONDS TO BACK-SIDE LANDS INCLUDING...

3D INTERCONNECT STRUCTURE COMPRISING THROUGH-SILICON VIAS COMBINED...

3D INTERCONNECT STRUCTURE COMPRISING THROUGH-SILICON VIAS COMBINED...

3D INTERCONNECT STRUCTURE COMPRISING FINE PITCH SINGLE DAMASCENE BA...

Under bump metallization layer to enable use of high tin content so...

UNDER BUMP METALLIZATION LAYER TO ENABLE USE OF HIGH TIN CONTENT SO...